> On 2011-01-17 00:58:49, Gabe Black wrote: > > I still don't totally follow why this is necessary, although I believe it > > probably is. One sticky problem you can run into with x86 (and probably > > most ISAs) is if you enable interrupts and then immediately disable them > > again, expecting that that will let any pent up interrupts get handled. Is > > it possible the CPU might attempt to process one but then lose it's > > opportunity in that case? I know in some real world case (I don't remember > > the specifics) it can hang an OS which expects an interrupt to get through > > as described and move things along. If that doesn't matter here then never > > mind, but it's a potential problem it would be best to fix if possible.
I think part of the problem here is that there's magical instantaneous communication about interrupts in most ISAs. Is that correct? If so, it would likely help for other ISAs to pass interrupts through the memory system like x86 does. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/338/#review744 ----------------------------------------------------------- On 2011-01-12 09:06:31, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/338/ > ----------------------------------------------------------- > > (Updated 2011-01-12 09:06:31) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fixes fetch deadlock when the interrupt clears before CPU handles it. > > When this condition occurs the cpu should restart the fetch stage to fetch > from > the original execution path. Fault handling in the commit stage is cleaned up > a > little bit so the control flow is simplier. Finally, if an instruction is > being > used to carry a fault it isn't executed, so the fault propigates > appropriately. > > > Diffs > ----- > > src/arch/arm/interrupts.hh 5d0f62927d75 > src/cpu/o3/commit.hh 5d0f62927d75 > src/cpu/o3/commit_impl.hh 5d0f62927d75 > src/cpu/o3/fetch.hh 5d0f62927d75 > src/cpu/o3/fetch_impl.hh 5d0f62927d75 > src/cpu/o3/iew_impl.hh 5d0f62927d75 > > Diff: http://reviews.m5sim.org/r/338/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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