> On 2011-01-17 09:01:22, Steve Reinhardt wrote: > > src/cpu/o3/fetch.hh, line 253 > > <http://reviews.m5sim.org/r/338/diff/2/?file=9499#file9499line253> > > > > This is a big improvement... seems like it would be even better if we > > could create a new ISA-dependent function like suppressInterrupts() that > > returns ((pc & 0x3) != 0) for the Alpha case and false for everyone else, > > then get rid of this function and change the original line to > > (interruptPending && !suppressInterrupts(pc)) > > which addresses my other concern, that checkInterrupt() is kind of > > unspecific since we already have a function called checkInterrupts(). > > Ali Saidi wrote: > I thought about creating one, but I couldn't decide what parameters > should be passed to it. Until we have another ISA that needs similar > functionality (and I'm not sure we will, I really don't know how to define a > function to handle the case, so I don't think there is a point in doing it.
I'm not a big fan of that sort of function either, primarily since it's really just moving the code around rather than factoring out it's ISA dependent-ness. I think the assumption that there's a PAL mode bit in the PC is one of the last widespread vestiges of the Alpha only days. It would be great to get rid of it, but in my experience that's been tricky to actually do. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/338/#review754 ----------------------------------------------------------- On 2011-01-12 09:06:31, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/338/ > ----------------------------------------------------------- > > (Updated 2011-01-12 09:06:31) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fixes fetch deadlock when the interrupt clears before CPU handles it. > > When this condition occurs the cpu should restart the fetch stage to fetch > from > the original execution path. Fault handling in the commit stage is cleaned up > a > little bit so the control flow is simplier. Finally, if an instruction is > being > used to carry a fault it isn't executed, so the fault propigates > appropriately. > > > Diffs > ----- > > src/arch/arm/interrupts.hh 5d0f62927d75 > src/cpu/o3/commit.hh 5d0f62927d75 > src/cpu/o3/commit_impl.hh 5d0f62927d75 > src/cpu/o3/fetch.hh 5d0f62927d75 > src/cpu/o3/fetch_impl.hh 5d0f62927d75 > src/cpu/o3/iew_impl.hh 5d0f62927d75 > > Diff: http://reviews.m5sim.org/r/338/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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