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Could you please explain the reason for this change? I'm not familiar enough with ARM's interrupt architecture to know what the commit message is saying. My guess is that the interrupt controller initially thought it was going to signal an interrupt but then later changed it's mind. If that's the case, then really shouldn't we change the interrupt controller so it doesn't change its mind? I don't that that's possible, but I can't think of why it wouldn't be. src/cpu/o3/iew_impl.hh <http://reviews.m5sim.org/r/338/#comment760> Shouldn't the instruction be a nop in this case and do nothing when executed? - Gabe On 2010-12-06 16:10:48, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/338/ > ----------------------------------------------------------- > > (Updated 2010-12-06 16:10:48) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fixes fetch deadlock when the interrupt master clears single before CPU > handles it. > Then the cpu should restart fetch stage to fetch from the original execution > path. > > > Diffs > ----- > > src/arch/arm/interrupts.hh 2b5fbdcbfb5d > src/cpu/o3/commit_impl.hh 2b5fbdcbfb5d > src/cpu/o3/fetch_impl.hh 2b5fbdcbfb5d > src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d > > Diff: http://reviews.m5sim.org/r/338/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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