----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/338/#review552 -----------------------------------------------------------
src/cpu/o3/commit_impl.hh <http://reviews.m5sim.org/r/338/#comment811> I think this code is evolving toward unnecessary complexity. It looks to me like there are two separate things going on: 1. calling cpu->checkInterrupts() to see if there are pending interrupts, and if so, initiating the pipeline flush and storing the interrupt code in the 'interrupt' variable 2. if the 'interrupt' variable is set and the pipeline is flushed, handling the interrupt Having both of these things combined in a single function that has to get called if either one of these things needs to be done is confusing. Is there even any need to store the interrupt fault code between 1 and 2? Seems like we just need a bool to remember that we passed 1 and are waiting for 2, and a few tests to see if either we arrived at 2 or the interrupt got cleared so we should roll back to a pre-1 state. src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/338/#comment810> I'm confused... in fetchCacheLine() we check (interruptPending && !(pc & 0x3)) and isSwitchedOut() and return false.... so what are the cases where fetchCacheLine returns true that need to be fixed up here? And aren't those cases that should be fixed up by making fetchCacheLine() return false rather than adding all these special checks here? src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/338/#comment806> Why not combine this info into a single DPRINTF? - Steve On 2010-12-06 16:10:48, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/338/ > ----------------------------------------------------------- > > (Updated 2010-12-06 16:10:48) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fixes fetch deadlock when the interrupt master clears single before CPU > handles it. > Then the cpu should restart fetch stage to fetch from the original execution > path. > > > Diffs > ----- > > src/arch/arm/interrupts.hh 2b5fbdcbfb5d > src/cpu/o3/commit_impl.hh 2b5fbdcbfb5d > src/cpu/o3/fetch_impl.hh 2b5fbdcbfb5d > src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d > > Diff: http://reviews.m5sim.org/r/338/diff > > > Testing > ------- > > > Thanks, > > Ali > >
_______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
