Hi, I am new to Gem-5 and I want to simulate and model L3 last level cache in gem-5 and then want to implement this last level cache as e-DRAM, STT-RAM. I have couple of questions as mentioned below:
1. If I want to simulate the behavior of last level caches for different memory technologies like e-DRAM, STT-RAM, 1T-SRAM for 8-core, 2GHz, OOO processor with 32KB, 8-way set assoc., 64 byte line size, 1 bank private L1 (I$ and D$), 256 KB, 8-way set assoc., 64 byte line size, 1 bank private L2$ and 32MB, 16way set assoc., 64 byte line size, 16 banks, write back shared L3 $. Should I go for ruby memory controller or classic memory controller? I have modified the "CacheConfig.py" for adding L3 cache hierarchy but now I am not sure whether there are other files apart from this which are needed to be modified for adding L3 cache and then how should I confirm whether the changes I have made are correct or not? 2. Could you please let me know that if I want to model e-DRAM or STT-RAM as last level L3 Cache, then which files should I need to modify because compared to SRAM cache these have different parameters like read latency, write latency, read energy, write energy, leakage power, refresh power? What I have figured out is that Ruby memory controller has a DRAM model (src/mem/ruby/system/RubyMemoryControl.cc) and parameters in (src/mem/ruby/system/RubyMemoryControl.py) but if I want a 3 level memory hierarchy then it is not supported in Ruby Memory model. Also does Ruby supports O3 CPU model? Any help or suggestion is greatly appreciated! Thanks Prateek _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
