Hi Prateek, The classic memory model has all the bits you need. There is a DRAM controller, and you can create as many levels of caches as you want (and stripe across as many different L3s as you please). You should be fine simply extending the fs.py or se.py script to make sure one or more L3s are inserted before the DRAM controllers.
When it comes to the specific cache configuration, you can create a subclass of the base cache, just like what is currently done for e.g. an L2Cache. To capture the idiosyncrasies of the various memory types you will most likely have to add functionality (adding a write-recovery time for example). I think this would be a great addition to gem5, and useful for a lot of people. Concerning the power and energy, you have to do these calculations off-line at the moment, simply using the stats from the simulation. Andreas On 03/04/2014 18:06, "Prateek Gupta" <[email protected]> wrote: >Hi, >I am new to Gem-5 and I want to simulate and model L3 last level cache in >gem-5 and then want to implement this last level cache as e-DRAM, >STT-RAM. I have couple of questions as mentioned below: > > >1. If I want to simulate the behavior of last level caches for different >memory technologies like e-DRAM, STT-RAM, 1T-SRAM for 8-core, 2GHz, OOO >processor with 32KB, 8-way set assoc., 64 byte line size, 1 bank private >L1 (I$ and D$), 256 KB, 8-way set assoc., 64 byte line size, 1 bank >private L2$ and 32MB, 16way set assoc., 64 byte line size, 16 banks, >write back shared L3 $. Should I go for ruby memory controller or classic >memory controller? I have modified the "CacheConfig.py" for adding L3 >cache hierarchy but now I am not sure whether there are other files apart >from this which are needed to be modified for adding L3 cache and then >how should I confirm whether the changes I have made are correct or not? > > >2. Could you please let me know that if I want to model e-DRAM or STT-RAM >as last level L3 Cache, then which files should I need to modify because >compared to SRAM cache these have different parameters like read latency, >write latency, read energy, write energy, leakage power, refresh power? >What I have figured out is that Ruby memory controller has a DRAM model >(src/mem/ruby/system/RubyMemoryControl.cc) and parameters in >(src/mem/ruby/system/RubyMemoryControl.py) but if I want a 3 level memory >hierarchy then it is not supported in Ruby Memory model. Also does Ruby >supports O3 CPU model? > >Any help or suggestion is greatly appreciated! > >Thanks >Prateek >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
