Hi Prateek,
It seems to look sensible. If you’re not getting the result you’re expecting
then I’d suggest stepping through the python code in more detail and add some
print/warn/inform statements here and there.
The dot (svg or pdf) output is handy to check what you specified, but it will
not help you debug where things are going wrong.
Andreas
From: Prateek Gupta <[email protected]<mailto:[email protected]>>
Reply-To: gem5 users mailing list
<[email protected]<mailto:[email protected]>>
Date: Friday, 4 April 2014 17:21
To: gem5-users <[email protected]<mailto:[email protected]>>
Subject: Re: [gem5-users] modeling L3 last level cache in gem5
Hello Andreas,
Thanks for your reply.
Do I need to extend fs.py or se.py? I have tried making changes in
CacheConfig.py, Caches.py and
Options.py as follows:
Options.py: I add this new option
parser.add_option("--l3cache", action="store_true")
Caches.py: I add the L3 cache
class L1Cache(BaseCache):
assoc = 8
hit_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
is_top_level = True
class L2Cache(BaseCache):
assoc = 8
hit_latency = 8
response_latency = 20
mshrs = 20
tgts_per_mshr = 16
write_buffers = 8
class L3Cache(BaseCache):
assoc = 16
hit_latency = 20
response_latency = 20
mshrs = 512
tgts_per_mshr = 20
write_buffers = 256
class IOCache(BaseCache):
assoc = 8
hit_latency = 50
response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
forward_snoops = False
is_top_level = True
class PageTableWalkerCache(BaseCache):
assoc = 2
hit_latency = 2
response_latency = 2
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
is_top_level = True
CacheConfig.py: The main changes are as follows:
import m5
from m5.objects import *
from Caches import *
from O3_ARM_v7a import *
def config_cache(options, system):
if options.cpu_type == "arm_detailed":
try:
from O3_ARM_v7a import *
except:
print "arm_detailed is unavailable. Did you compile the O3
model?"
sys.exit(1)
dcache_class, icache_class, l2_cache_class, l3_cache_class = \
O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, O3_ARM_v7aL3
else:
dcache_class, icache_class, l2_cache_class, l3_cache_class = \
L1Cache, L1Cache, L2Cache, L3Cache
# Set the cache line size of the system
system.cache_line_size = options.cacheline_size
if options.l3cache:
system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l3_size,
assoc=options.l3_assoc)
system.tol3bus = CoherentBus(clk_domain = system.cpu_clk_domain,
width = 32)
system.l3.cpu_side = system.tol3bus.master
system.l3.mem_side = system.membus.slave
else:
if options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs, and set the L1-to-L2 bus width to 32
# bytes (256 bits).
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc)
system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
width = 32)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
for i in xrange(options.num_cpus):
if options.caches:
icache = icache_class(size=options.l1i_size,
assoc=options.l1i_assoc)
dcache = dcache_class(size=options.l1d_size,
assoc=options.l1d_assoc)
if options.l3cache:
system.cpu[i].l2 = l2_cache_class(size=options.l2_size,
assoc=options.l2_assoc)
system.cpu[i].tol2bus = CoherentBus()
system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
system.cpu[i].l2.mem_side = system.tol3bus.slave
# When connecting the caches, the clock is also inherited
# from the CPU in question
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(),
PageTableWalkerCache())
else:
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
system.cpu[i].createInterruptController()
if options.l3cache:
system.cpu[i].connectAllPorts(system.cpu[i].tol3bus,
system.membus)
else:
if options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
else:
system.cpu[i].connectAllPorts(system.membus)
return system
I am not getting any changes in the results in config.dot.py and stats.txt from
when I am simulating without making the changes for L3 caches, I am wondering
whether I have missed something?
Thanks,
Prateek
On 04/03/14, "Prateek Gupta" wrote:
> Hi,
> I am new to Gem-5 and I want to simulate and model L3 last level cache in
> gem-5 and then want to implement this last level cache as e-DRAM, STT-RAM. I
> have couple of questions as mentioned below:
>
>
> 1. If I want to simulate the behavior of last level caches for different
> memory technologies like e-DRAM, STT-RAM, 1T-SRAM for 8-core, 2GHz, OOO
> processor with 32KB, 8-way set assoc., 64 byte line size, 1 bank private L1
> (I$ and D$), 256 KB, 8-way set assoc., 64 byte line size, 1 bank private L2$
> and 32MB, 16way set assoc., 64 byte line size, 16 banks, write back shared L3
> $. Should I go for ruby memory controller or classic memory controller? I
> have modified the "CacheConfig.py" for adding L3 cache hierarchy but now I am
> not sure whether there are other files apart from this which are needed to be
> modified for adding L3 cache and then how should I confirm whether the
> changes I have made are correct or not?
>
>
> 2. Could you please let me know that if I want to model e-DRAM or STT-RAM as
> last level L3 Cache, then which files should I need to modify because
> compared to SRAM cache these have different parameters like read latency,
> write latency, read energy, write energy, leakage power, refresh power? What
> I have figured out is that Ruby memory controller has a DRAM model
> (src/mem/ruby/system/RubyMemoryControl.cc) and parameters in
> (src/mem/ruby/system/RubyMemoryControl.py) but if I want a 3 level memory
> hierarchy then it is not supported in Ruby Memory model. Also does Ruby
> supports O3 CPU model?
>
> Any help or suggestion is greatly appreciated!
>
> Thanks
> Prateek
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