Hi Prateek, I'm trying to do something very similar to what you were. Would you please let me know what was the if-else ladder problem that you were mentioning? I'm a bit stuck at this point and would appreciate any help on this.
Thanks, Poovaiah On Wed, Apr 9, 2014 at 12:25 PM, Prateek Gupta <[email protected]> wrote: > Hi all, > > I have added the write latency parameter using patch 2072 in gem 5 for > simulating stt-ram behavior as L3 cache in gem5. There are visible changes > in gem5 results when I am changing the write latency in desired proportion > for stt-ram but I am not seeing any changes in McPAT results for power > after integrating gem-5 and mcpat. Are there any changes required in > memorycontrol.cc or cachecontroller.cc files of Mcpat also for L3 cache to > get L3 results in McPAT or should I need to make any changes in .xml files > manually for changing the parameter values for L3?? > > > Thanks, > Prateek > University of Wisconsin-Madison > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Poovaiah MP
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
