On 4/20/2023 11:33 AM, Eliot Moss via gem5-users wrote:
On 4/20/2023 10:58 AM, 中国石油大学张天 via gem5-users wrote:
Hello everyone, I would like to ask, when executing non memory access instructions in Gem5,
shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented, how
is this instruction executed?
gem5 does not model at the circuit level. A piece of C++ code,
defined with the instruction, will perform the operation. It
charges an indicated amount of time, according to the functional
unit. gem5 deals with all the queueing and timing, but does not
model at the gate level.
Best wishes - EM
It occurred to me to add a little bit to this. The out-of-order (O3)
cpu model allows you define a bunch of different functional units,
which ones can handle which instructions, how many of each the cpu
has, their timing, etc. For that model anyway there is no single
"ALU". What I said above still holds: gem5 defines enough to be
able to determine timing (and an estimate of power consumption) but
it does not model at a more detailed level than that.
The model of DRAM chips is somewhat more detailed and realistic
(perhaps), but that's necessary to get obtain accurate timing
predictions.
HTH -- EM
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