On 4/20/2023 12:20 PM, 中国石油大学张天 via gem5-users wrote:
Okay, thank you. I have received your suggestion and I will think it over tomorrow. It's already midnight here, so I'll go to bed first 😊。 Thank you again. By the way, it seems that every time I send you an email, you always reject it.
If you mean I am always saying "that's not a concept in gem5", then I am just trying to be honest. There's nothing wrong with playing around with a residual based ALU. I just don't see how it makes any sense in gem5 because of the level at which it models things. You might be able to connect such a hardware model up, invoke it whenever an instruction comes along that wants to use it, and plug the result back in, but what would that really accomplish, assuming it is just an alternative implementation (at the gate level) of existing instructions? They aren't modeled at the gate level anyway. Maybe it would stress test your model, but assuming the mode is correct, I suspect all it would do is dramatically slow down the simulation. May be I/we could be more helpful if you could clarify your broader goal, what you're trying to accomplish, and why you think gem5 is a good vehicle for it. If I am just totally misunderstanding, I apologize. Regards - EM _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
