On 15/06/16 17:17, Jonas Baggett wrote:
Hello,
I can have a look at the bug tracker and work on the FST waveforms
dumper. What needs to be done ?
I have just started to work on dumping enums in FST.
But records are still missing. It would also be nice to be able to
select signals to be dumped.
If I understand well, making à python interface will allow to simulate a
system with some parts written in vhdl and other parts written in
python. And also if there would be a simulink clone written in python,
you could for example modelize à motor with it and then simulate the
motor with its controller written in vhdl, right ?
My first idea was to expose the semantic of a VHDL design in python, so
that users could write their own tools in python.
But there are many other possibilities.
Tristan.
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