On Thu, Jun 16, 2016 at 8:27 AM, Martin Strubel <hack...@section5.ch> wrote:
> Hi there, > > >>> My first idea was to expose the semantic of a VHDL design in python, so > >>> that users could write their own tools in python. > >>> But there are many other possibilities. > >> > >> Do you mean creating an interface to allow a tool in python to access > >> e.g. signals deep inside the design and let it read or write it's value > ? > > > > Yes, but not only during simulation. Being also possible to generate a > > C interface from an entity, to extract sensitivity from a process... > > Something like VHPI but in python. > > > > It would be very powerful, if a simulation could be started from within > MyHDL and speak with it. It sounds like the myhdl team needs to revisit the VHPI interface, when we last looked (many years ago) it was incomplete. It seems probable that the latest GHDL VHPI would support the MyHDL cosimulation requirements. Regards, Chris
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