Hi there, >>> My first idea was to expose the semantic of a VHDL design in python, so >>> that users could write their own tools in python. >>> But there are many other possibilities. >> >> Do you mean creating an interface to allow a tool in python to access >> e.g. signals deep inside the design and let it read or write it's value ? > > Yes, but not only during simulation. Being also possible to generate a > C interface from an entity, to extract sensitivity from a process... > Something like VHPI but in python. >
It would be very powerful, if a simulation could be started from within MyHDL and speak with it. Currently, I have to do loads of workarounds with ghdlex and netpp to 'export' VHDL entities to the network. This could all be nicely offloaded to Python and pickled instances can be transferred over the network as well. Especially if Python objects could be constructed at runtime. For example, a Wishbone Bus entity could then be accessed as: w = ghdl_export.entities['Wb_inst0'] # Access by name w.addr.set(0x80002) w.data.set(0xdeadbeef) w.write_strobe() However, if a working entity is present, the signals will of course collide/interfere. I kinda hacked this with a gated clock which is interrupted, whenever the external software probe connects. Not nice, there has to be a proper "way to do it". This just for inspiration...maybe there is a better concept. Scanning the hierarchy actually works as of now, but using the VPI interface which I found less powerful, there's issues with threading and I couldn't figure a way to make it work synchronously (to the VHDL simulation) unlike the VHPI side. Cheers, - Martin _______________________________________________ Ghdl-discuss mailing list Ghdl-discuss@gna.org https://mail.gna.org/listinfo/ghdl-discuss
