On 15/06/16 23:29, Jonas Baggett wrote:
Le 15.06.16 18:37, Tristan Gingold a écrit :
On 15/06/16 17:17, Jonas Baggett wrote:
Hello,
I can have a look at the bug tracker and work on the FST waveforms
dumper. What needs to be done ?
I have just started to work on dumping enums in FST.
But records are still missing. It would also be nice to be able to
select signals to be dumped.
My first thoughts about signals selection would be to let the user
create a file containing a list of the signals he wants to be displayed
like this :
top_level_instance/sub_entity_instance/sub_sub_entity_instance/the_signal.
He could also display all the signals of an entity like this :
top_level_instance/sub_entity_instance/*. To display all the signal of
an entity and recursively to all of it's sub entities :
top_level_instance/sub_entity_instance/**. Maybe I can add the
possibility to write something like this :
top_level_instance/sub_entity_instance/<port> versus
top_level_instance/sub_entity_instance/<architecture> to show all the
signals only in port respectively only in architecture.
That looks good. I like the use of '*' and '**'.
That's only the first ideas, the format may change. Then I will create a
simulation option to allow the user to pass the file in parameter. The
--disp-tree simulation option will help the user to find the full path
of a signal or an entity instance.
If I understand well, making à python interface will allow to simulate a
system with some parts written in vhdl and other parts written in
python. And also if there would be a simulink clone written in python,
you could for example modelize à motor with it and then simulate the
motor with its controller written in vhdl, right ?
My first idea was to expose the semantic of a VHDL design in python, so
that users could write their own tools in python.
But there are many other possibilities.
Do you mean creating an interface to allow a tool in python to access
e.g. signals deep inside the design and let it read or write it's value ?
Yes, but not only during simulation. Being also possible to generate a
C interface from an entity, to extract sensitivity from a process...
Something like VHPI but in python.
Tristan.
_______________________________________________
Ghdl-discuss mailing list
Ghdl-discuss@gna.org
https://mail.gna.org/listinfo/ghdl-discuss