Hi all,
open source synthesis is fine. Can be quite independent of the
target device, with limited knowledge of it one can get probably
quite far. Using such a tool to generate a netlist and the vendor
tool chains for implementation ((place and route) and bitstream
generation might be worth a try.
But for the implementation step and bitstream generation, as tried
in icestorm, one needs a very precise timing model and lots of other
very deep knowledge about the target device. And in case of a mistake
in implementation one can easily burn up an FPGA.
And to your question: simulation, as done by ghdl, and synthesis, as
done by Yosys, are very different things. They both start with a
parser for the input language (VHDL), but that's in fact the simplest
part.
With best regards, Walter
On 10/03/2016 06:21 PM, Salvador Eduardo Tropea wrote:
Hi All!
Last year the first free software tool chain for FPGAs emerged. The IceStorm
(http://www.clifford.at/icestorm/) project allows
synthesis from Verilog for Lattice iCE40 FPGAs.
This tool-chain uses Yosys (http://www.clifford.at/yosys/) as base.
But no VHDL. Recently Yodl (https://github.com/forflo/yodl) emerged. Yodl is an
effort to do what Yosys does for Verilog, but for VHDL.
I'm a complete ignorant about GHDL, Yosys and Yodl internals, but I'm curious
about the synergy between GHDL and Yodl.
I know GHDL is ADA code and I see Yodl is C++. But I see Yodl people having
some problems (or doubts) about the VHDL parser.
Just wondering ...
Regards, Salvador
P.D: I know IceStorm currently support
http://www.edautils.com/vhdl2verilog.html and this is an incomplete solution.
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