Synthesis and simulation are indeed completely different things.

There are a few Verilog-to-VHDL tools such as
vhdl2verilog http://www.edautils.com/vhdl2verilog.html
vhd2vl http://doolittle.icarus.com/~larry/vhd2vl/
vhdlpp https://github.com/steveicarus/iverilog/tree/master/vhdlpp
But all of them could implement their own, limited VHDL parser.
Limited as much in syntax checking and in functionalities and
conversion abilities.

As VHDL is a programming language with complicated features, I
think that parsing it is in fact a challenge.
Being able to reuse a good parser would be very helpful, and there
is no doubt GHDL's is the best out there in the open-source world.
Also, existing code introspection features certainly strongly help
conversion, for translation to Verilog as well as doing synthesis:
executing functions that just generate constants or do casts, etc.

Even if you consider that as the "simplest" part, it's still a big
part, and any reuse of good stuff would saves a lot of
reinvent-the-wheel time and allow to better focus on the the rest.


On Mon, 2016-10-03 at 19:18 +0200, Walter F.J. Mueller wrote:
> Hi all,
> open source synthesis is fine. Can be quite independent of the
> target device, with limited knowledge of it one can get probably
> quite far. Using such a tool to generate a netlist and the vendor
> tool chains for implementation ((place and route) and bitstream
> generation might be worth a try.
> But for the implementation step and bitstream generation, as tried
> in icestorm, one needs a very precise timing model and lots of other
> very deep knowledge about the target device. And in case of a mistake
> in implementation one can easily burn up an FPGA.
> And to your question: simulation, as done by ghdl, and synthesis, as
> done by Yosys, are very different things. They both start with a
> parser for the input language (VHDL), but that's in fact the simplest
> part.
> >     With best regards,      Walter
> On 10/03/2016 06:21 PM, Salvador Eduardo Tropea wrote:
> > 
> > Hi All!
> > 
> > > > Last year the first free software tool chain for FPGAs emerged. The 
> > > > IceStorm (http://www.clifford.at/icestorm/)  project allows
> > synthesis from Verilog for Lattice iCE40 FPGAs.
> > 
> > > > This tool-chain uses Yosys (http://www.clifford.at/yosys/) as base.
> > 
> > > > But no VHDL. Recently Yodl (https://github.com/forflo/yodl) emerged. 
> > > > Yodl is an effort to do what Yosys does for Verilog, but for VHDL.
> > 
> > I'm a complete ignorant about GHDL, Yosys and Yodl internals, but I'm 
> > curious about the synergy between GHDL and Yodl.
> > 
> > I know GHDL is ADA code and I see Yodl is C++. But I see Yodl people having 
> > some problems (or doubts) about the VHDL parser.
> > 
> > Just wondering ...
> > 
> > Regards, Salvador
> > 
> > P.D: I know IceStorm currently support 
> > http://www.edautils.com/vhdl2verilog.html and this is an incomplete 
> > solution.
> > 
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