On 17/10/16 11:29, Martin Strubel wrote:


Hi Tristan,


Comments and suggestions are welcome.

1) Cool stuff! That might come in very handy for Co-Simulation and other
code analysis
2) Could you post a simple example XML output of a FF/register
assignment (only if you have the nerve for it, of course), e.g.

process(clk)
begin
    if rising_edge(clk) then
    if en = '1' then
            r0 <= r1;
        end if;
    end if;
end process;

The interesting part of the xml is:

              <concurrent_statement_chain>
<el id="830" kind="sensitized_process_statement" file="ex.vhdl"
                 line="12" col="3" label="" seen_flag="false"
                 end_has_postponed="false" passive_flag="false"
                 postponed_flag="false" visible_flag="false"
                 is_within_flag="false" has_label="false" has_is="false"
                 end_has_reserved_id="true" end_has_identifier="false"
                 wait_state="unknown">
                  <parent ref="826"/>
                  <sequential_statement_chain>
<el id="832" kind="if_statement" file="ex.vhdl" line="14" col="5" label="" suspend_flag="false" visible_flag="false"
                     end_has_identifier="false">
                      <parent ref="830"/>
<condition id="999" kind="function_call" file="ex.vhdl"
                       line="14" col="8" expr_staticness="none"
                       name_staticness="none">
                        <prefix id="833" kind="simple_name" file="ex.vhdl"
                         line="14" col="8" identifier="rising_edge"
                         is_forward_ref="false" expr_staticness="???"
                         name_staticness="???">
                          <type ref="18"/>
                          <named_entity ref="1272"/>
                          <base_name ref="1272"/>
                        </prefix>
                        <type ref="18"/>
                        <parameter_association_chain>
<el id="836" kind="association_element_by_expression"
                           file="ex.vhdl" line="14" col="20"
                           whole_association_flag="true"
                           collapse_signal_flag="false">
<actual id="835" kind="simple_name" file="ex.vhdl"
                             line="14" col="20" identifier="clk"
                             is_forward_ref="false" expr_staticness="none"
                             name_staticness="local">
                              <type ref="940"/>
                              <named_entity ref="815"/>
                              <base_name ref="815"/>
                            </actual>
                          </el>
                        </parameter_association_chain>
                        <implementation ref="1272"/>
                        <base_name ref="999"/>
                      </condition>
                      <sequential_statement_chain>
                        <el id="837" kind="if_statement" file="ex.vhdl"
                         line="15" col="5" label="" suspend_flag="false"
                         visible_flag="false" end_has_identifier="false">
                          <parent ref="832"/>
                          <condition id="839" kind="equality_operator"
                           file="ex.vhdl" line="15" col="11"
                           expr_staticness="none">
                            <type ref="18"/>
<left id="838" kind="simple_name" file="ex.vhdl"
                             line="15" col="8" identifier="en"
                             is_forward_ref="false" expr_staticness="none"
                             name_staticness="local">
                              <type ref="940"/>
                              <named_entity ref="818"/>
                              <base_name ref="818"/>
                            </left>
                            <implementation ref="1296"/>
                            <right id="840" kind="character_literal"
file="ex.vhdl" line="15" col="13" identifier="'1'"
                             is_forward_ref="false" expr_staticness="local"
                             name_staticness="local">
                              <type ref="940"/>
                              <named_entity ref="944"/>
                              <base_name ref="944"/>
                            </right>
                          </condition>
                          <sequential_statement_chain>
                            <el id="842"
                             kind="simple_signal_assignment_statement"
                             file="ex.vhdl" line="16" col="13" label=""
delay_mechanism="inertial" visible_flag="false"
                             guarded_target_state="false">
                              <parent ref="837"/>
                              <target id="841" kind="simple_name"
                               file="ex.vhdl" line="16" col="13"
                               identifier="r0" is_forward_ref="false"
expr_staticness="none" name_staticness="local">
                                <type ref="940"/>
                                <named_entity ref="822"/>
                                <base_name ref="822"/>
                              </target>
                              <waveform_chain>
                                <el id="843" kind="waveform_element"
                                 file="ex.vhdl" line="16" col="19">
                                  <we_value id="844" kind="simple_name"
                                   file="ex.vhdl" line="16" col="19"
                                   identifier="r1" is_forward_ref="false"
                                   expr_staticness="none"
                                   name_staticness="local">
                                    <type ref="940"/>
                                    <named_entity ref="820"/>
                                    <base_name ref="820"/>
                                  </we_value>
                                </el>
                              </waveform_chain>
                            </el>
                          </sequential_statement_chain>
                        </el>
                      </sequential_statement_chain>
                    </el>
                  </sequential_statement_chain>
                  <sensitivity_list list-id="13">
<el id="829" kind="simple_name" file="ex.vhdl" line="12"
                     col="11" identifier="clk" is_forward_ref="false"
                     expr_staticness="none" name_staticness="local">
                      <type ref="940"/>
                      <named_entity ref="815"/>
                      <base_name ref="815"/>
                    </el>
                  </sensitivity_list>
                </el>
              </concurrent_statement_chain>

3) Someone mentioned a schema (XSD), this sounds like an awful lot of
work to me, esp. at an early stage, when things might change. I'd rather
see many conversion examples.

I have never written XSD, to I cannot really comment.

4) I was wondering, if it was actually possible to hack an .XSL to
extract register assignments as the above, or if a more complex tree
parsing via a "real" programming language was required.

I fear that xsl is not the best way to write a syntheziser...

Tristan.


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