On 11/10/16 15:45, Salvador Eduardo Tropea wrote:
A note to make things more clear: Yosys converts Verilog into an AST,
GHDL also does it. The point is: if we manage to convert GHDL's AST into
the Yosys AST we get a VHDL synthesis tool ;-)
That's not so easy because the AST are very different.
I think it would be simpler to directly generate a pre-netlist from GHDL
AST.
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