Hello,
I have just added a new command to dump the AST tree in XML:
ghdl --file-to-xml FILEs
The output can be very large (XML is not compact, and even std.standard
is not small). See iirs.ads for documentation of the fields.
Enjoy (or not).
Comments and suggestions are welcome.
Tristan.
As an example, the XML part for:
architecture behav of simple1 is
signal s : bit;
begin
s <= '1';
process
begin
report "Start of simple1" severity note;
assert s = '0' severity failure;
wait for 0 ns;
assert s = '1' severity failure;
wait;
end process;
end behav;
is:
<library_unit id="826" kind="architecture_body"
file="simple1.vhdl"
line="4" col="14" identifier="behav" foreign_flag="false"
visible_flag="true" is_within_flag="false"
end_has_reserved_id="false" end_has_identifier="true">
<parent ref="824"/>
<entity_name id="817" kind="simple_name" file="simple1.vhdl"
line="4" col="23" identifier="simple1"
is_forward_ref="false"
expr_staticness="???" name_staticness="???">
<named_entity ref="822"/>
</entity_name>
<declaration_chain>
<el id="828" kind="signal_declaration" file="simple1.vhdl"
line="5" col="10" identifier="s"
has_disconnect_flag="false"
has_active_flag="false" has_identifier_list="false"
visible_flag="true" after_drivers_flag="false"
use_flag="false" is_ref="false"
guarded_signal_flag="false"
signal_kind="bus" expr_staticness="none"
name_staticness="local">
<parent ref="826"/>
<subtype_indication id="829" kind="simple_name"
file="simple1.vhdl" line="5" col="14" identifier="bit"
is_forward_ref="false" expr_staticness="???"
name_staticness="???">
<type ref="25"/>
<named_entity ref="54"/>
<base_name ref="54"/>
</subtype_indication>
<type ref="25"/>
</el>
</declaration_chain>
<concurrent_statement_chain>
<el id="832" kind="concurrent_simple_signal_assignment"
file="simple1.vhdl" line="7" col="3" label=""
delay_mechanism="inertial" postponed_flag="false"
visible_flag="false" guarded_target_state="false">
<parent ref="826"/>
<target id="830" kind="simple_name" file="simple1.vhdl"
line="7" col="3" identifier="s" is_forward_ref="false"
expr_staticness="none" name_staticness="local">
<type ref="25"/>
<named_entity ref="828"/>
<base_name ref="828"/>
</target>
<waveform_chain>
<el id="831" kind="waveform_element"
file="simple1.vhdl"
line="7" col="8">
<we_value id="834" kind="character_literal"
file="simple1.vhdl" line="7" col="8"
identifier="'1'"
is_forward_ref="false" expr_staticness="local"
name_staticness="local">
<type ref="25"/>
<named_entity ref="53"/>
<base_name ref="53"/>
</we_value>
</el>
</waveform_chain>
</el>
<el id="836" kind="process_statement" file="simple1.vhdl"
line="9" col="3" label="" seen_flag="false"
end_has_postponed="false" suspend_flag="true"
passive_flag="false" postponed_flag="false"
visible_flag="false" is_within_flag="false"
has_label="false"
has_is="false" end_has_reserved_id="true"
end_has_identifier="false" wait_state="unknown">
<parent ref="826"/>
<sequential_statement_chain>
<el id="835" kind="report_statement"
file="simple1.vhdl"
line="11" col="5" label="" visible_flag="false">
<parent ref="836"/>
<severity_expression id="839" kind="simple_name"
file="simple1.vhdl" line="11" col="40"
identifier="note"
is_forward_ref="false" expr_staticness="local"
name_staticness="local">
<type ref="345"/>
<named_entity ref="358"/>
<base_name ref="358"/>
</severity_expression>
<report_expression id="838" kind="string_literal8"
file="simple1.vhdl" line="11" col="12"
string_length="16" has_signed="false"
has_sign="false"
has_length="false" bit_string_base="BASE_NONE"
expr_staticness="local">
<string8_id length="16" content="Start of
simple1"/>
<literal_subtype id="860"
kind="array_subtype_definition"
file="simple1.vhdl"
line="11" col="12" resolved_flag="false"
signal_type_flag="true" has_signal_flag="false"
index_constraint_flag="true"
type_staticness="local"
constraint_state="fully constrained">
<index_constraint_list list-id="16">
<el id="856" kind="integer_subtype_definition"
file="simple1.vhdl" line="11" col="12"
resolved_flag="false" signal_type_flag="false"
has_signal_flag="false" is_ref="false"
type_staticness="local">
<range_constraint id="857"
kind="range_expression" file="simple1.vhdl"
line="11" col="12" expr_staticness="local"
direction="to">
<right_limit_expr id="858"
kind="integer_literal" file="simple1.vhdl"
line="11" col="12" value=" 16"
expr_staticness="local">
<type ref="647"/>
</right_limit_expr>
<type ref="647"/>
<left_limit ref="650"/>
<right_limit ref="858"/>
</range_constraint>
<base_type ref="399"/>
</el>
</index_constraint_list>
<index_subtype_list list-ref="16"/>
<element_subtype ref="84"/>
<base_type ref="654"/>
</literal_subtype>
<type ref="860"/>
</report_expression>
</el>
<el id="840" kind="assertion_statement"
file="simple1.vhdl"
line="12" col="5" label="" visible_flag="false">
<parent ref="836"/>
<assertion_condition id="842"
kind="equality_operator"
file="simple1.vhdl" line="12" col="14"
expr_staticness="none">
<type ref="18"/>
<left id="841" kind="simple_name"
file="simple1.vhdl"
line="12" col="12" identifier="s"
is_forward_ref="false" expr_staticness="none"
name_staticness="local">
<type ref="25"/>
<named_entity ref="828"/>
<base_name ref="828"/>
</left>
<implementation ref="58"/>
<right id="843" kind="character_literal"
file="simple1.vhdl" line="12" col="16"
identifier="'0'" is_forward_ref="false"
expr_staticness="local" name_staticness="local">
<type ref="25"/>
<named_entity ref="52"/>
<base_name ref="52"/>
</right>
</assertion_condition>
<severity_expression id="844" kind="simple_name"
file="simple1.vhdl" line="12" col="29"
identifier="failure" is_forward_ref="false"
expr_staticness="local" name_staticness="local">
<type ref="345"/>
<named_entity ref="361"/>
<base_name ref="361"/>
</severity_expression>
</el>
<el id="846" kind="wait_statement" file="simple1.vhdl"
line="13" col="5" label="" visible_flag="false">
<parent ref="836"/>
<timeout_clause id="845" kind="physical_int_literal"
file="simple1.vhdl" line="13" col="14" value=" 0"
expr_staticness="global">
<physical_unit ref="565"/>
<unit_name id="848" kind="simple_name"
file="simple1.vhdl" line="13" col="16"
identifier="ns"
is_forward_ref="false" expr_staticness="global"
name_staticness="local">
<type ref="559"/>
<named_entity ref="565"/>
<base_name ref="565"/>
</unit_name>
<type ref="559"/>
</timeout_clause>
</el>
<el id="849" kind="assertion_statement"
file="simple1.vhdl"
line="14" col="5" label="" visible_flag="false">
<parent ref="836"/>
<assertion_condition id="851"
kind="equality_operator"
file="simple1.vhdl" line="14" col="14"
expr_staticness="none">
<type ref="18"/>
<left id="850" kind="simple_name"
file="simple1.vhdl"
line="14" col="12" identifier="s"
is_forward_ref="false" expr_staticness="none"
name_staticness="local">
<type ref="25"/>
<named_entity ref="828"/>
<base_name ref="828"/>
</left>
<implementation ref="58"/>
<right id="852" kind="character_literal"
file="simple1.vhdl" line="14" col="16"
identifier="'1'" is_forward_ref="false"
expr_staticness="local" name_staticness="local">
<type ref="25"/>
<named_entity ref="53"/>
<base_name ref="53"/>
</right>
</assertion_condition>
<severity_expression id="853" kind="simple_name"
file="simple1.vhdl" line="14" col="29"
identifier="failure" is_forward_ref="false"
expr_staticness="local" name_staticness="local">
<type ref="345"/>
<named_entity ref="361"/>
<base_name ref="361"/>
</severity_expression>
</el>
<el id="854" kind="wait_statement" file="simple1.vhdl"
line="15" col="5" label="" visible_flag="false">
<parent ref="836"/>
</el>
</sequential_statement_chain>
</el>
</concurrent_statement_chain>
</library_unit>
On 11/10/16 20:37, Adrien Prost-Boucle wrote:
On Tue, 2016-10-11 at 19:57 +0200, Tristan Gingold wrote:
On 11/10/16 15:45, Salvador Eduardo Tropea wrote:
A note to make things more clear: Yosys converts Verilog into an AST,
GHDL also does it. The point is: if we manage to convert GHDL's AST into
the Yosys AST we get a VHDL synthesis tool ;-)
That's not so easy because the AST are very different.
I think it would be simpler to directly generate a pre-netlist from GHDL
AST.
Of course, AST to AST is not easy.
However GHDL does parse VHDL, checks syntax, provides and handles libs, finds
and parses components, etc.
That's a huge burden for projects that currently have to start and re-do that
from scratch,
having to redesign the wheel(s) in the process and certainly achieving much
less coverage and overall quality and efficiency.
Moreover, when we need a parser it's in most cases to do something that is not
directly related to it, but still _needs_ it.
The development time needed to have half of a parser is high and not rewarding
since it's a component and not the core of the target tool.
For comparison:
There are frequent changes to the CLang AST and to the corresponding API,
nonetheless it's of very widespead use as C/C++ parser.
I'm developer of an HLS tool (C -> VHDL) and I can guarantee that the parser is
an unavoidable _key_ component.
The quality and versatility of the parser is a prerequisite to a huge amount of
functionalities in the tool that uses it.
A badly designed parser is a heavy drag that triggers a lot of suffering and is
often a blocker, trust me.
Adrien
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