Hi Tristan,
Comments and suggestions are welcome.
1) Cool stuff! That might come in very handy for Co-Simulation and other
code analysis
2) Could you post a simple example XML output of a FF/register
assignment (only if you have the nerve for it, of course), e.g.
process(clk)
begin
if rising_edge(clk) then
if en = '1' then
r0 <= r1;
end if;
end if;
end process;
3) Someone mentioned a schema (XSD), this sounds like an awful lot of
work to me, esp. at an early stage, when things might change. I'd rather
see many conversion examples.
4) I was wondering, if it was actually possible to hack an .XSL to
extract register assignments as the above, or if a more complex tree
parsing via a "real" programming language was required.
I'm working a lot with XML to create HDL and other sources, it took
quite a while to design the dialect such that the translation overhead
is not too massive (IP-XACT not being the best example here...)
But this topic is definitely different, more like disassembly, so I
guess the next story (where the XSD makes sense) would be the design of
the transfer language, i.e. apart from the pure analysis aspect, being
able to identify FF/Muxer/LUT and other primitives and translate them
into some mid level XML RTL, that again would translate to a netlist
usable by the mapper tools.
But the big gordian knot might be, to keep this layer independent of the
FPGA technology (assuming that the HDL design is free of vendor specifics).
Cheers,
- Strubi
_______________________________________________
Ghdl-discuss mailing list
Ghdl-discuss@gna.org
https://mail.gna.org/listinfo/ghdl-discuss
