@cousteaulecommandant pushed 6 commits. 09d250da7145b7a0083af1a8f5065150b8035921 tagmanager: SystemVerilog: map ctags 2fff652c169e708408ff5b4ebc4f85d69867a9c4 tagmanager: Unify Verilog and SystemVerilog tags 1e023bcce748fadf794188b63f600930b9cf5dac Split SystemVerilog keywords into type / not type 19d9250f7f9d7183191f189c4f0670826a77cd20 Add missing SystemVerilog tasks/functions 1ff70710453d66639456362a26027bee24e046af Regenerate Verilog ctags unit tests 41fb57391229ca678446c101b5cc5b50eb226c3a Add SystemVerilog ctags unit tests
-- View it on GitHub: https://github.com/geany/geany/pull/4039/files/e4f7c7241306a61d569317dd9f5b748cba541536..41fb57391229ca678446c101b5cc5b50eb226c3a You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/4039/before/e4f7c7241306a61d569317dd9f5b748cba541536/after/[email protected]>
