It has been done. Hooray! @techee: there's only one issue pending which is whether it is OK to leave the comments I put in `group_SYSVERILOG` or if I should remove those as well.
I also re-generated the ctags unit tests for Verilog and added two for SystemVerilog. While doing so, I noticed a couple of issues/bugs in ctags (I think), but those should be fixed in ctags. I left the points of failure marked in comments in the unit tests. Other than this, the PR is ready to go. -- Reply to this email directly or view it on GitHub: https://github.com/geany/geany/pull/4039#issuecomment-2483955601 You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/4039/[email protected]>
