@cousteaulecommandant pushed 7 commits. 4ad90857cf94f8f0628f0eaeb440c06d070231db Add SystemVerilog filetype bee6076de639bcadd57eef4afd426e4e20cb1a32 tagmanager: SystemVerilog: map ctags 66710b09699d416e024574bb744f80ebe09eb186 tagmanager: Unify Verilog and SystemVerilog tags 85564aa10dbdc8b2e47354d913c797f39fd5c4fa Split SystemVerilog keywords into type / not type b26b7fc801316433683848da3b5d558cafcd8e5d Add missing SystemVerilog tasks/functions e7a215ddedc345e06a1878705c037b6694467868 Regenerate Verilog ctags unit tests 4b7c56e5f482d2fb562fe81bd45b8641c5642828 Add SystemVerilog ctags unit tests
-- View it on GitHub: https://github.com/geany/geany/pull/4039/files/2560628da808b9ce4658b294749ec4eae5731d93..4b7c56e5f482d2fb562fe81bd45b8641c5642828 You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/4039/before/2560628da808b9ce4658b294749ec4eae5731d93/after/[email protected]>
