Thanks for that.
I would like to add, that I was working for a customer which has
the first coding at very many places in almost every module,
because it is included in a global macro. The problem with modern
processors is,
that if the location PTR to store the address is in the same cache line
(that is,
less than 256 byte apart from the place where the ST operation is), you
will get
the I-cache invalidated, which leads to severe performance issues. The
customer
observed this by significant performance degradation in the LPAR where
those ASSEMBLER programs are running. We then had to rework
(at least recompile, after macro change) all these several thousand
programs
to remedy the problem.
The problem is known as SIIS (store into instruction stream).
Kind regards
Bernd
Am 08.02.2021 um 03:38 schrieb Seymour J Metz:
This is refreshable, and even runs on S/360
L R15,PTR
LTR R15,R15
BNZ CALLIT
... ... Code that always
leaves the same value in R15
ST R15,PTR
CALLIT BALR R14,R15
...
PTR DC A(0)
This is reentrant, and requires at least S/370
RETRY L R1,COUNTER
LA R0,1(,R1)
CS R1,,R0,COUNTER
BNE RETRY
...
COUNTER DC F'0'
I would consider either to be bad form.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
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