Apples and Oranges ... The final chip fab is usually the product of an underlying chip designed set with additional customization.
Apple's M1 chip is a great example.... it is licensed ARM chip arch with lots of enhancements. So it is the M1 built on an ARM. The way chips have been designed for several years now, is to use a set library of functions and pick and choose what you need. For example, from the ARM library, you take 4 performance cores, 2 efficient cores, 2 GPUs, a storage manager, interrupt controller, and PCIe for a start... Then add 4M of L0 cache for each CPU, 32M L1 cache shared, and a 16G main storage and a 512G PCIe SSD ... all on the single chip carrier. There were also enhancements added to facility Intel Emulation since they knew they had to support both native ARM instructs and run an emulator for all the existing Intel applications. Rosetta 2 Note: Apple did the same when they transitioned from the Power to Intel... Rosetta The Power CPUs are a great RISC engine. There were other projects in Apple at one time that had HPUX and AIX running on an Apple Power PC that never saw daylight ... But it is still an ARM ... Intel's Xeon and Core chips are also RISC engines with X64 firmware ... Why do you think we get firmware patches to correct Xeon or Core instruction issues. From a pure engineering stand, it would make sense to use the Power library as a foundation since they already owned the proven tech. Use it as a fast microcontroller, RISC engine, and add the additional functionality they needed to implement the zArch instruction set. That CHIP and Firmware would be uniquely a z-CHIP but at its heart is probably a Power engine. But it is just a guess. When you couple the development of the z with the other two product lines, it is reasonable to assert that there is commonality there. Money being the driving force. It is also possible that the zArch engineers took an earlier version of the Power library and made it their own. Who actually knows what goes on that deep within IBM. Take the Z apart ... the Channel Cards, the IOP, the Storage books, the OSA, the PCIe interfaces, the Books that make up the CPUs, etc. This is a still a collection of microcontrollers working together to implement the z/Arch. It would also make good business sense that IBM would share as much tech as possible between the product lines of i-Server, p-Server and z-Server... in order to save costs. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
