On Mon, 26 Sep 2011 13:38:26 -0700, Kenneth Graunke <[email protected]> wrote: > On 09/26/2011 01:31 PM, Daniel Vetter wrote: > > On Mon, Sep 26, 2011 at 11:59:23AM -0700, Kenneth Graunke wrote: > >> +static int > >> +gen6_render_ring_flush(struct intel_ring_buffer *ring, > >> + u32 invalidate_domains, u32 flush_domains) > >> +{ > >> + u32 flags = 0; > >> + struct pipe_control *pc = ring->private; > >> + u32 scratch_addr = pc->gtt_offset + 128; > >> + int ret; > >> + > >> + /* Force SNB workarounds for PIPE_CONTROL flushes */ > >> + intel_emit_post_sync_nonzero_flush(ring); > >> + > >> + /* Just flush everything for now */ > >> + flags |= PIPE_CONTROL_WC_FLUSH; > >> + flags |= PIPE_CONTROL_IS_FLUSH; > >> + flags |= PIPE_CONTROL_TC_FLUSH; > >> + flags |= PIPE_CONTROL_DEPTH_FLUSH; > >> + flags |= PIPE_CONTROL_VFC; > > > > Any reason you're not also setting the constant cache and state cache > > invalidate bits? > > -Daniel > > Bits 2 and 3? No particular reason; perhaps they should be.
IIRC we're not using the constant cache today, but it would be nice to, so let's get it set. We definitely need state cache invalidate.
pgpets6uhHzKv.pgp
Description: PGP signature
_______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
