From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 26 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h        | 10 ++++++----
 drivers/gpu/drm/i915/i915_pci.c        | 14 ++++++++++++++
 3 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms 
b/drivers/gpu/drm/i915/Kconfig.platforms
index 1302eb3989be..1fe95996879a 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -141,3 +141,29 @@ config DRM_I915_PLATFORM_INTEL_SANDYBRIDGE
        help
          Include support for Intel Sandybridge platforms.
 
+config DRM_I915_GEN7
+       bool
+
+config DRM_I915_PLATFORM_INTEL_IVYBRIDGE
+       bool "Intel Ivybridge platform support"
+       default y
+       depends on DRM_I915
+       select DRM_I915_GEN7
+       help
+         Include support for Intel Ivybridge platforms.
+
+config DRM_I915_PLATFORM_INTEL_VALLEYVIEW
+       bool "Intel Valleyview platform support"
+       default y
+       depends on DRM_I915
+       select DRM_I915_GEN7
+       help
+         Include support for Intel Valleyview platforms.
+
+config DRM_I915_PLATFORM_INTEL_HASWELL
+       bool "Intel Haswell platform support"
+       default y
+       depends on DRM_I915
+       select DRM_I915_GEN7
+       help
+         Include support for Intel Haswell platforms.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 311ddb8009b4..9025658bada7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2599,12 +2599,12 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_G33(dev_priv)       IS_OPT_PLATFORM(dev_priv, INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)        (IS_OPT_PLATFORM(dev_priv, 
INTEL_IRONLAKE) && \
                                 (INTEL_DEVID(dev_priv) == 0x0046))
-#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
+#define IS_IVYBRIDGE(dev_priv) IS_OPT_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 #define IS_IVB_GT1(dev_priv)   (IS_IVYBRIDGE(dev_priv) && \
                                 (dev_priv)->info.gt == 1)
-#define IS_VALLEYVIEW(dev_priv)        IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
+#define IS_VALLEYVIEW(dev_priv)        IS_OPT_PLATFORM(dev_priv, 
INTEL_VALLEYVIEW)
 #define IS_CHERRYVIEW(dev_priv)        IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
-#define IS_HASWELL(dev_priv)   IS_PLATFORM(dev_priv, INTEL_HASWELL)
+#define IS_HASWELL(dev_priv)   IS_OPT_PLATFORM(dev_priv, INTEL_HASWELL)
 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
 #define IS_SKYLAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
 #define IS_BROXTON(dev_priv)   IS_PLATFORM(dev_priv, INTEL_BROXTON)
@@ -2732,7 +2732,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN6(dev_priv) \
        (IS_ENABLED(CONFIG_DRM_I915_GEN6) && \
         ((dev_priv)->info.gen_mask & BIT(5)))
-#define IS_GEN7(dev_priv)      (!!((dev_priv)->info.gen_mask & BIT(6)))
+#define IS_GEN7(dev_priv) \
+       (IS_ENABLED(CONFIG_DRM_I915_GEN7) && \
+        ((dev_priv)->info.gen_mask & BIT(6)))
 #define IS_GEN8(dev_priv)      (!!((dev_priv)->info.gen_mask & BIT(7)))
 #define IS_GEN9(dev_priv)      (!!((dev_priv)->info.gen_mask & BIT(8)))
 #define IS_GEN10(dev_priv)     (!!((dev_priv)->info.gen_mask & BIT(9)))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8a7399787f4b..205a8fc5e8be 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -322,6 +322,7 @@ static const struct intel_device_info 
intel_sandybridge_m_gt2_info = {
        .platform = INTEL_IVYBRIDGE, \
        .has_l3_dpf = 1
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_IVYBRIDGE
 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
        IVB_D_PLATFORM,
        .gt = 1,
@@ -331,6 +332,7 @@ static const struct intel_device_info 
intel_ivybridge_d_gt2_info = {
        IVB_D_PLATFORM,
        .gt = 2,
 };
+#endif
 
 #define IVB_M_PLATFORM \
        GEN7_FEATURES, \
@@ -338,6 +340,7 @@ static const struct intel_device_info 
intel_ivybridge_d_gt2_info = {
        .is_mobile = 1, \
        .has_l3_dpf = 1
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_IVYBRIDGE
 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
        IVB_M_PLATFORM,
        .gt = 1,
@@ -355,7 +358,9 @@ static const struct intel_device_info 
intel_ivybridge_q_info = {
        .num_pipes = 0, /* legal, last one wins */
        .has_l3_dpf = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_VALLEYVIEW
 static const struct intel_device_info intel_valleyview_info = {
        .platform = INTEL_VALLEYVIEW,
        .gen = 7,
@@ -375,6 +380,7 @@ static const struct intel_device_info intel_valleyview_info 
= {
        GEN_DEFAULT_PIPEOFFSETS,
        CURSOR_OFFSETS
 };
+#endif
 
 #define G75_FEATURES  \
        GEN7_FEATURES, \
@@ -392,6 +398,7 @@ static const struct intel_device_info intel_valleyview_info 
= {
        .platform = INTEL_HASWELL, \
        .has_l3_dpf = 1
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_HASWELL
 static const struct intel_device_info intel_haswell_gt1_info = {
        HSW_PLATFORM,
        .gt = 1,
@@ -406,6 +413,7 @@ static const struct intel_device_info 
intel_haswell_gt3_info = {
        HSW_PLATFORM,
        .gt = 3,
 };
+#endif
 
 #define GEN8_FEATURES \
        G75_FEATURES, \
@@ -685,15 +693,21 @@ static const struct pci_device_id pciidlist[] = {
        INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
        INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
 #endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_IVYBRIDGE
        INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
        INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
        INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
        INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
        INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_HASWELL
        INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
        INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
        INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_VALLEYVIEW
        INTEL_VLV_IDS(&intel_valleyview_info),
+#endif
        INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
        INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
        INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
-- 
2.14.1

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