> -----Original Message-----
> From: Intel-xe <[email protected]> On Behalf Of
> Animesh Manna
> Sent: Tuesday, February 3, 2026 7:14 PM
> To: [email protected]; [email protected]
> Cc: Dibin Moolakadan Subrahmanian
> <[email protected]>; Nikula, Jani
> <[email protected]>; Manna, Animesh <[email protected]>
> Subject: [PATCH v2 07/10] drm/i915/cmtg: program sync to port for cmtg
* CMTG
>
> Program Cmtg Sync to Port Sync. Set before enabling the timing generator.
> While cmtg start running this bit will be cleared.
* CMTG
Bspec link
>
> Signed-off-by: Animesh Manna <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 3 +++
> drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 12a081dd7e4d..3af4aefc760e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -258,4 +258,7 @@ void intel_cmtg_enable(const struct intel_crtc_state
> *crtc_state)
> intel_de_read(display,
> TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
>
> intel_cpu_cmtg_transcoder_set_m_n(crtc_state);
> +
> + /* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
> + intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index b766ded8686c..0ed767a797c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -18,7 +18,9 @@
>
> #define TRANS_CMTG_CTL_A _MMIO(0x6fa88)
> #define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
> +#define TRANS_CMTG_CTL(id) _MMIO(0x6fa88 + (id) * 0x100)
What's the point of defining TRANS_CMTG_CTL_A/B if you are not going to use it
Also have a look at how _TRANS_MMIO works
Use that a lot of you register definitions can use that without having to use a
formula for
Every def.
Regards,
Suraj Kandpal
> #define CMTG_ENABLE REG_BIT(31)
> +#define CMTG_SYNC_TO_PORT REG_BIT(29)
>
> #define TRANS_HTOTAL_CMTG(id) _MMIO(0x6F000 + (id) *
> 0x100)
> #define TRANS_HBLANK_CMTG(id) _MMIO(0x6F004 + (id) *
> 0x100)
> --
> 2.29.0
