Make intel_set_transcoder_timings_lrr() take the target transcoder as an explicit parameter instead of always using crtc_state->cpu_transcoder. This allows the LRR timing programming sequence to be reused for other transcoders (e.g. CMTG).
Move the intel_vrr_set_fixed_rr_timings() and intel_vrr_transcoder_enable() calls out of intel_set_transcoder_timings_lrr() and into its only caller intel_pipe_fastset(), so the helper now strictly programs the LRR timing registers for the given transcoder. No functional change intended. Signed-off-by: Animesh Manna <[email protected]> --- drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2c15dd4c6d66..17621f66501f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2777,14 +2777,14 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta } } -static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state) +static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state, + enum transcoder transcoder) { struct intel_display *display = to_intel_display(crtc_state); - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; - drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); + drm_WARN_ON(display->drm, transcoder_is_dsi(transcoder)); crtc_vdisplay = adjusted_mode->crtc_vdisplay; crtc_vtotal = adjusted_mode->crtc_vtotal; @@ -2799,7 +2799,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc if (DISPLAY_VER(display) >= 13) { intel_de_write(display, - TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder), + TRANS_SET_CONTEXT_LATENCY(display, transcoder), crtc_state->set_context_latency); /* @@ -2816,7 +2816,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode. * But let's write it anyway to keep the state checker happy. */ - intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), + intel_de_write(display, TRANS_VBLANK(display, transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); /* @@ -2832,12 +2832,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc * The double buffer latch point for TRANS_VTOTAL * is the transcoder's undelayed vblank. */ - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), + intel_de_write(display, TRANS_VTOTAL(display, transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); - - intel_vrr_set_fixed_rr_timings(crtc_state); - intel_vrr_transcoder_enable(crtc_state); } static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) @@ -6674,8 +6671,11 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, &new_crtc_state->dp_m_n); - if (new_crtc_state->update_lrr) - intel_set_transcoder_timings_lrr(new_crtc_state); + if (new_crtc_state->update_lrr) { + intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state->cpu_transcoder); + intel_vrr_set_fixed_rr_timings(new_crtc_state); + intel_vrr_transcoder_enable(new_crtc_state); + } } static void commit_pipe_pre_planes(struct intel_atomic_state *state, -- 2.29.0
