Program the VRR registers of CMTG, as the VRR timing generator will always be enabled for NVL.
Add intel_cmtg_set_vrr_timings() which mirrors the per-transcoder VRR VMIN/VMAX/FLIPLINE programming on the CMTG transcoder paired with the pipe's cpu_transcoder. Invoke it from intel_vrr_set_transcoder_timings() and from the LRR fastset path, right after the existing intel_vrr_set_fixed_rr_timings() calls, so the CMTG VRR timing registers stay in sync with the cpu_transcoder's. v2: Use sw state instead of reading from hardware. [Jani] v3: Program cmtg vrr timing registers along with vrr transcoder registers. v4: Reuse vrr timing programming helper. Bspec: 68989 Signed-off-by: Animesh Manna <[email protected]> --- drivers/gpu/drm/i915/display/intel_cmtg.c | 11 +++++++++++ drivers/gpu/drm/i915/display/intel_cmtg.h | 1 + drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++ 4 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c index 082c04bec9ee..4c8187ddef1f 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg.c +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c @@ -16,6 +16,7 @@ #include "intel_display_power.h" #include "intel_display_regs.h" #include "intel_display_types.h" +#include "intel_vrr.h" /** * DOC: Common Primary Timing Generator (CMTG) @@ -244,3 +245,13 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr) else intel_set_transcoder_timings(crtc_state, cmtg_transcoder); } + +void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state) +{ + enum transcoder cmtg_transcoder = to_cmtg_transcoder(crtc_state->cpu_transcoder); + + if (!intel_cmtg_is_allowed(crtc_state)) + return; + + intel_vrr_set_fixed_rr_timings(crtc_state, cmtg_transcoder); +} diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h index 53a44f505dd2..899a2744514c 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg.h +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h @@ -11,6 +11,7 @@ struct intel_display; struct intel_crtc_state; +void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state); void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr); void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state); void intel_cmtg_sanitize(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 416dea9e0d36..56769a2c7f72 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6675,6 +6675,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, intel_set_transcoder_timings_lrr(new_crtc_state, new_crtc_state->cpu_transcoder); intel_cmtg_set_timings(new_crtc_state, true); intel_vrr_set_fixed_rr_timings(new_crtc_state, new_crtc_state->cpu_transcoder); + intel_cmtg_set_vrr_timings(new_crtc_state); intel_vrr_transcoder_enable(new_crtc_state); } } diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 15d22de66d63..2295f6545981 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -7,6 +7,7 @@ #include <drm/drm_print.h> #include "intel_alpm.h" +#include "intel_cmtg.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_regs.h" @@ -646,6 +647,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) } intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder); + intel_cmtg_set_vrr_timings(crtc_state); if (!intel_vrr_always_use_vrr_tg(display)) intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), -- 2.29.0
