> -----Original Message-----
> From: Manna, Animesh <[email protected]>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: [email protected]; [email protected]
> Cc: Shankar, Uma <[email protected]>; Dibin Moolakadan Subrahmanian
> <[email protected]>; [email protected];
> Nikula, Jani <[email protected]>; Manna, Animesh
> <[email protected]>
> Subject: [PATCH v8 05/20] drm/i915/display: Skip DP_MIN_HBLANK_CTL
> programming for CMTG transcoders
>
> DP_MIN_HBLANK_CTL is a CPU transcoder register and must not be written for
> the CMTG transcoders. Skip the programming when the target transcoder is
> TRANSCODER_CMTG0 or TRANSCODER_CMTG1.
Looks Good to me.
Reviewed-by: Uma Shankar <[email protected]>
> Signed-off-by: Animesh Manna <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9031264a34fc..2c15dd4c6d66 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2761,7 +2761,9 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
> VACTIVE(crtc_vdisplay - 1) |
> VTOTAL(crtc_vtotal - 1));
>
> - if (DISPLAY_VER(display) >= 30) {
> + if (DISPLAY_VER(display) >= 30 &&
> + transcoder != TRANSCODER_CMTG0 &&
> + transcoder != TRANSCODER_CMTG1) {
> /*
> * Address issues for resolutions with high refresh rate that
> * have small Hblank, specifically where Hblank is smaller than
> --
> 2.29.0
