Hi,
It seems I missed one condition while setting enable bit for WM's,
because of which It's not enabling WM level-0 & you are observing flickers.
I'll upload updated patch.
On Monday 12 September 2016 06:41 PM, Maarten Lankhorst wrote:
Hey,
Op 09-09-16 om 10:01 schreef Kumar, Mahesh:
From: Mahesh Kumar <mahesh1.ku...@intel.com>
This patch implements new DDB allocation algorithm as per HW team
suggestion. This algo takecare of scenario where we allocate less DDB
for the planes with lower relative pixel rate, but they require more DDB
to work.
It also takes care of enabling same watermark level for each
plane, for efficient power saving.
Changes since v1:
- Rebase on top of Paulo's patch series
This breaks the kms_atomic_transition testcase. I'm getting a lot of CPU pipe
(A,B,C) FIFO underrun error messages,
and my DP-MST display won't turn on at all.
~Maarten
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