From: Antonios Motakis <[email protected]> We can reuse the code under hypervisor/arch/arm/mmu_cell.c for the AArch64 port, save for the value we use for the VTCRL. AArch64 will need in addition to the flags set by the AArch32 port, to set the size of the address space.
We put this behind a define in asm/paging.h to allow this reuse. Signed-off-by: Antonios Motakis <[email protected]> --- hypervisor/arch/arm/include/asm/paging.h | 6 ++++++ hypervisor/arch/arm/mmu_cell.c | 7 +------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/hypervisor/arch/arm/include/asm/paging.h b/hypervisor/arch/arm/include/asm/paging.h index 98fc343..0afbc86 100644 --- a/hypervisor/arch/arm/include/asm/paging.h +++ b/hypervisor/arch/arm/include/asm/paging.h @@ -120,6 +120,12 @@ #define TCR_SL0_SHIFT 6 #define TCR_S_SHIFT 4 +#define VTCR_CELL (T0SZ | SL0 << TCR_SL0_SHIFT \ + | (TCR_RGN_WB_WA << TCR_IRGN0_SHIFT) \ + | (TCR_RGN_WB_WA << TCR_ORGN0_SHIFT) \ + | (TCR_INNER_SHAREABLE << TCR_SH0_SHIFT)\ + | VTCR_RES1) + /* * Hypervisor memory attribute indexes: * 0: normal WB, RA, WA, non-transient diff --git a/hypervisor/arch/arm/mmu_cell.c b/hypervisor/arch/arm/mmu_cell.c index fb5ad83..d3031de 100644 --- a/hypervisor/arch/arm/mmu_cell.c +++ b/hypervisor/arch/arm/mmu_cell.c @@ -77,12 +77,7 @@ int arch_mmu_cpu_cell_init(struct per_cpu *cpu_data) struct cell *cell = cpu_data->cell; unsigned long cell_table = paging_hvirt2phys(cell->arch.mm.root_table); u64 vttbr = 0; - u32 vtcr = T0SZ - | SL0 << TCR_SL0_SHIFT - | (TCR_RGN_WB_WA << TCR_IRGN0_SHIFT) - | (TCR_RGN_WB_WA << TCR_ORGN0_SHIFT) - | (TCR_INNER_SHAREABLE << TCR_SH0_SHIFT) - | VTCR_RES1; + u32 vtcr = VTCR_CELL; if (cell->id > 0xff) { panic_printk("No cell ID available\n"); -- 2.8.0.rc3 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
