From: Antonios Motakis <[email protected]> Hide TLB flushes issues by the MMU code behind a macro, so we can increase our chances of reusing some of this code.
Signed-off-by: Antonios Motakis <[email protected]> --- hypervisor/arch/arm/include/asm/processor.h | 2 ++ hypervisor/arch/arm/mmu_cell.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hypervisor/arch/arm/include/asm/processor.h b/hypervisor/arch/arm/include/asm/processor.h index c6144a7..907a28e 100644 --- a/hypervisor/arch/arm/include/asm/processor.h +++ b/hypervisor/arch/arm/include/asm/processor.h @@ -197,6 +197,8 @@ static inline bool is_el2(void) return (psr & PSR_MODE_MASK) == PSR_HYP_MODE; } +#define tlb_flush_guest() arm_write_sysreg(TLBIALL, 1) + #endif /* !__ASSEMBLY__ */ #endif /* !_JAILHOUSE_ASM_PROCESSOR_H */ diff --git a/hypervisor/arch/arm/mmu_cell.c b/hypervisor/arch/arm/mmu_cell.c index d3031de..d16c5ea 100644 --- a/hypervisor/arch/arm/mmu_cell.c +++ b/hypervisor/arch/arm/mmu_cell.c @@ -107,7 +107,7 @@ void arch_cpu_tlb_flush(struct per_cpu *cpu_data) * Invalidate all stage-1 and 2 TLB entries for the current VMID * ERET will ensure completion of these ops */ - arm_write_sysreg(TLBIALL, 1); + tlb_flush_guest(); dsb(nsh); cpu_data->flush_vcpu_caches = false; } -- 2.8.0.rc3 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
