From: Jan Kiszka <[email protected]> Just to be safe: ICC_SGI1R_EL1 allows us to address at most 16 cores in the most significant affinity level. Encode this restriction in the init code because we will rely on it during runtime.
Signed-off-by: Jan Kiszka <[email protected]> --- hypervisor/arch/arm/gic-v3.c | 4 ++++ hypervisor/arch/arm/include/asm/sysregs.h | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hypervisor/arch/arm/gic-v3.c b/hypervisor/arch/arm/gic-v3.c index 9732085c..4987e2bc 100644 --- a/hypervisor/arch/arm/gic-v3.c +++ b/hypervisor/arch/arm/gic-v3.c @@ -118,6 +118,10 @@ static int gic_cpu_init(struct per_cpu *cpu_data) return -ENODEV; } + /* Make sure we can handle Aff0 with the TargetList of ICC_SGI1R_EL1. */ + if ((cpu_data->mpidr & MPIDR_AFF0_MASK) >= 16) + return trace_error(-EIO); + /* Ensure all IPIs and the maintenance PPI are enabled. */ mmio_write32(redist_base + GICR_SGI_BASE + GICR_ISENABLER, 0x0000ffff | (1 << mnt_irq)); diff --git a/hypervisor/arch/arm/include/asm/sysregs.h b/hypervisor/arch/arm/include/asm/sysregs.h index e65adc45..a6266586 100644 --- a/hypervisor/arch/arm/include/asm/sysregs.h +++ b/hypervisor/arch/arm/include/asm/sysregs.h @@ -57,8 +57,9 @@ #define CTR_EL0 SYSREG_32(0, c0, c0, 1) #define MPIDR_EL1 SYSREG_32(0, c0, c0, 5) #define MPIDR_CPUID_MASK 0x00ffffff -#define MPIDR_MP_BIT (1 << 31) +#define MPIDR_AFF0_MASK 0x000000ff #define MPIDR_U_BIT (1 << 30) +#define MPIDR_MP_BIT (1 << 31) #define ID_PFR0_EL1 SYSREG_32(0, c0, c1, 0) #define ID_PFR1_EL1 SYSREG_32(0, c0, c1, 1) #define PFR1_VIRT(pfr) ((pfr) >> 12 & 0xf) -- 2.12.3 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
