From: Jan Kiszka <[email protected]> No more users of arm_cpu_phys2virt/virt2phys are remaining, so we can purge the code from related fragments.
Signed-off-by: Jan Kiszka <[email protected]> --- hypervisor/arch/arm-common/irqchip.c | 6 ------ hypervisor/arch/arm/control.c | 32 ++---------------------------- hypervisor/arch/arm/include/asm/percpu.h | 8 -------- hypervisor/arch/arm/setup.c | 1 - hypervisor/arch/arm64/control.c | 20 ------------------- hypervisor/arch/arm64/include/asm/percpu.h | 14 ------------- 6 files changed, 2 insertions(+), 79 deletions(-) diff --git a/hypervisor/arch/arm-common/irqchip.c b/hypervisor/arch/arm-common/irqchip.c index 3c86a10a..a4bcfbf4 100644 --- a/hypervisor/arch/arm-common/irqchip.c +++ b/hypervisor/arch/arm-common/irqchip.c @@ -150,12 +150,6 @@ void gic_handle_sgir_write(struct sgi *sgi, bool affinity_routing) continue; } else { /* - * When using a cpu map to target the different - * CPUs (GICv2), they are independent from the - * physical CPU IDs, so there is no need to - * translate them to the hypervisor's virtual - * IDs. - * * If we end up here in GICv3 mode, ie. with * affinity routing enabled, the cpu map will * be empty, and we will do nothing - just like diff --git a/hypervisor/arch/arm/control.c b/hypervisor/arch/arm/control.c index 1dfd6169..1934ae4c 100644 --- a/hypervisor/arch/arm/control.c +++ b/hypervisor/arch/arm/control.c @@ -171,35 +171,14 @@ struct registers* arch_handle_exit(struct per_cpu *cpu_data, return regs; } -unsigned int arm_cpu_virt2phys(struct cell *cell, unsigned int virt_id) -{ - unsigned int cpu; - - for_each_cpu(cpu, cell->cpu_set) { - if (per_cpu(cpu)->virt_id == virt_id) - return cpu; - } - - return -1; -} - int arch_cell_create(struct cell *cell) { int err; - unsigned int cpu; - unsigned int virt_id = 0; err = arm_paging_cell_init(cell); if (err) return err; - /* - * Generate a virtual CPU id according to the position of each CPU in - * the cell set - */ - for_each_cpu(cpu, cell->cpu_set) - per_cpu(cpu)->virt_id = virt_id++; - err = irqchip_cell_init(cell); if (err) { arm_paging_cell_destroy(cell); @@ -214,18 +193,11 @@ int arch_cell_create(struct cell *cell) void arch_cell_destroy(struct cell *cell) { unsigned int cpu; - struct per_cpu *percpu; arm_cell_dcaches_flush(cell, DCACHE_INVALIDATE); - for_each_cpu(cpu, cell->cpu_set) { - percpu = per_cpu(cpu); - - /* Re-assign the physical IDs for the root cell */ - percpu->virt_id = percpu->cpu_id; - - percpu->cpu_on_entry = PSCI_INVALID_ADDRESS; - } + for_each_cpu(cpu, cell->cpu_set) + per_cpu(cpu)->cpu_on_entry = PSCI_INVALID_ADDRESS; mach_cell_exit(cell); irqchip_cell_exit(cell); diff --git a/hypervisor/arch/arm/include/asm/percpu.h b/hypervisor/arch/arm/include/asm/percpu.h index d8b10fce..14cf3e13 100644 --- a/hypervisor/arch/arm/include/asm/percpu.h +++ b/hypervisor/arch/arm/include/asm/percpu.h @@ -40,7 +40,6 @@ struct per_cpu { unsigned long linux_reg[NUM_ENTRY_REGS]; unsigned int cpu_id; - unsigned int virt_id; /* synchronizes parallel insertions of SGIs into the pending ring */ spinlock_t pending_irqs_lock; @@ -131,13 +130,6 @@ static inline struct registers *guest_regs(struct per_cpu *cpu_data) return (struct registers *)(cpu_data->stack + sizeof(cpu_data->stack) - sizeof(struct registers)); } - -static inline unsigned int arm_cpu_phys2virt(unsigned int cpu_id) -{ - return per_cpu(cpu_id)->virt_id; -} - -unsigned int arm_cpu_virt2phys(struct cell *cell, unsigned int virt_id); #endif /* !__ASSEMBLY__ */ #endif /* !_JAILHOUSE_ASM_PERCPU_H */ diff --git a/hypervisor/arch/arm/setup.c b/hypervisor/arch/arm/setup.c index 7f358998..0aedbf9e 100644 --- a/hypervisor/arch/arm/setup.c +++ b/hypervisor/arch/arm/setup.c @@ -73,7 +73,6 @@ int arch_cpu_init(struct per_cpu *cpu_data) { int err; - cpu_data->virt_id = cpu_data->cpu_id; cpu_data->mpidr = phys_processor_id(); /* diff --git a/hypervisor/arch/arm64/control.c b/hypervisor/arch/arm64/control.c index ce78439b..788ebc63 100644 --- a/hypervisor/arch/arm64/control.c +++ b/hypervisor/arch/arm64/control.c @@ -117,23 +117,3 @@ void arch_cell_destroy(struct cell *cell) arm_paging_cell_destroy(cell); } - -/* - * We get rid of the virt_id in the AArch64 implementation, since it - * doesn't really fit with the MPIDR CPU identification scheme on ARM. - * - * Until the GICv3 and ARMv7 code has been properly refactored to - * support this scheme, we stub this call so we can share the GICv2 - * code with ARMv7. - * - * TODO: implement MPIDR support in the GICv3 code, so it can be - * used on AArch64. - * TODO: refactor out virt_id from the AArch7 port as well. - */ -unsigned int arm_cpu_phys2virt(unsigned int cpu_id) -{ - panic_printk("FATAL: we shouldn't reach here\n"); - panic_stop(); - - return -EINVAL; -} diff --git a/hypervisor/arch/arm64/include/asm/percpu.h b/hypervisor/arch/arm64/include/asm/percpu.h index 5bfece6d..9c437faf 100644 --- a/hypervisor/arch/arm64/include/asm/percpu.h +++ b/hypervisor/arch/arm64/include/asm/percpu.h @@ -111,20 +111,6 @@ static inline struct registers *guest_regs(struct per_cpu *cpu_data) return (struct registers *)(cpu_data->stack + sizeof(cpu_data->stack) - sizeof(struct registers)); } - -/* - * We get rid of the virt_id in the AArch64 implementation, since it - * doesn't really fit with the MPIDR CPU identification scheme on ARM. - * - * Until the GICv3 and ARMv7 code has been properly refactored to - * support this scheme, we stub this call so we can share the GICv2 - * code with ARMv7. - * - * TODO: implement MPIDR support in the GICv3 code, so it can be - * used on AArch64. - * TODO: refactor out virt_id from the AArch7 port as well. - */ -unsigned int arm_cpu_phys2virt(unsigned int cpu_id); #endif /* !__ASSEMBLY__ */ #endif /* !_JAILHOUSE_ASM_PERCPU_H */ -- 2.12.3 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. 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