On Mon, Aug 07, 2017 at 09:07:46PM +0300, Thanos Baloukas wrote:
> On 07/08/2017 07:09 μμ, Bruce Dubbs wrote:

> My suspicion was that if Ryzens have new instructions, and gcc did not
> fully adjust yet, some packages compiled on a Ryzen could use some
> optimization options that might cause illegal instruction trouble
> on other cpus. That is a totally hypothetical and may be totally wrong
> as well. Also it's not related at all to the thread that Ken posted and
> the problems it describes.
> 
> > In addition, the rather long thread I read indicated that the problem
> > was erratic.  Users would repeatedly compile mesa (or other packages) in
> > a loop and it would fail at random iterations.  That points to HW.
> > 
> > My best guess that the problem is some sort of complex timing problem
> > between the processor and it's support chips.
> > 
According to phoronix, the problem has been confirmed, which I guess
means it is a little closer to getting fixed.

https://www.phoronix.com/scan.php?page=news_item&px=Ryzen-Segv-Response

They occur with many parallel compilation workloads.  But that's our
(devs, testers) reason for justifying our hardware isn't it.

ĸen
-- 
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everything is a duck as far as I'm concerned.  -- Monstrous Regiment
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