As you noticed the FSMC is the only thing on AHB3. The Disco puts a framebuffer in there and uses the LCD_TFT peripheral to dump it out to an LCD at 60hz. My original design I've got an FPGA hanging off the FSMC with a DDR2 memory controller and an HDMI MAC (to drive the SIL HDMI Phy chip) prototyping that part is being done on a Zedboard (which uses a Zynq FPGA). My alternate is a Spartan3 with a VGA port and an SDRAM memory controller (the parts for that as an FPGA doing 1280 x 800 is about $8). Using the FSMC timing pins and making the SDRAM prioritize to the video you get glitchless video (its pretty nice actually). But you really don't want to run code in that SDRAM as gets a bunch of wait states if the video is refreshing. One thing you can do though is build a simple L1 cache in the FPGA to give the CPU and the framebuffer access to the same RAM space with minimal conflict.
Of course with the 429 you get an SDRAM controller on the chip, so now I'm thinking two banks of SDRAM one of which is eligible for frame buffer stuff and one of which is just for code. Could be a pretty simple system with the potential to do some pretty cool stuff but fairly cheaply and fully documented. --Chuck On Sat, Feb 1, 2014 at 9:14 PM, skeezix <[email protected]> wrote: > On Sat, 1 Feb 2014, skeezix wrote: > > # "Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled > # memory) data RAMUp to 192+4 Kbytes of SRAM including 64- Kbyte of CCM > # (core coupled memory) data RAM" > # > # Which is to say, SRAM 112K, SRAM 16K, and CCM 64K. There is no > # SRAM3 on the F405. > > You know, the problem for me is GPIOs _and_ SRAM; they're all on > AHB1, along with DMA 1 and 2. So basicly any time I want to use any GPIO, > while DMA is going on, my image will glitch. Anytime I load SRAM1 during > DMA, it'll glitch. > > FSMC is on AHB3, interestingly.. so I could perhaps tie into the > Z80 RAM chip, and with timing games access the RAM there and communicate > via RAM. Keep a action log in a buffer in memory, so the Z80 can issue > instructions in RAM. Then my main loop can just take a peek at RAM and > away it goes. (The Z80 clock may actually be driven by a timer in the > STM32 here so that is is software adjustable.. in which case I can just > hit the RAM after the clock ticks, or suspend the clock some number of > uSecs every scanline, whatever.) > > The U(S)ARTs and I2C are on another bus as well, so the > intermediary chip would work fine as well. Could have DMA1 from USART to > SRAM2, and have the 16K there work as an action log as well. > > I'll have to meditate on it; the self imposed rule of talking to a > z80 is the real problem here, since it lacks i2c/etc. > > I'll take it off the mailing list for a few days while I wrap my > head around it; no need to derail the list any more than I have :) > > But feel free to write back (perhaps directly to me?) if you think > FSMC to mount the z80 ram might be a neat hack. > > jeff > > -- > If everyone would put barbecue sauce on their food, there would be no war. > > ------------------------------------------------------------------------------ > WatchGuard Dimension instantly turns raw network data into actionable > security intelligence. It gives you real-time visual feedback on key > security issues and trends. Skip the complicated setup - simply import > a virtual appliance and go from zero to informed in seconds. > http://pubads.g.doubleclick.net/gampad/clk?id=123612991&iu=/4140/ostg.clktrk > _______________________________________________ > libopencm3-devel mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/libopencm3-devel ------------------------------------------------------------------------------ WatchGuard Dimension instantly turns raw network data into actionable security intelligence. It gives you real-time visual feedback on key security issues and trends. Skip the complicated setup - simply import a virtual appliance and go from zero to informed in seconds. http://pubads.g.doubleclick.net/gampad/clk?id=123612991&iu=/4140/ostg.clktrk _______________________________________________ libopencm3-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/libopencm3-devel
