ChromeART isn't on all the f4s so I've ignored it; I think the flags you found would help alleviate contention at the cost of dma performance and I can't mess with timings :/
I can slow it down a touch as I've got some borders, widening it probably makes dma contention worse :) Kids bugging me, can't concentrate :) Jeff -- Have you played Atari today? > On Feb 1, 2014, at 5:08 PM, Paul Sokolovsky <[email protected]> wrote: > > Hello, > > On Fri, 31 Jan 2014 13:34:50 -0500 (EST) > skeezix <[email protected]> wrote: > > [] > >> But timing (say) a screen blit DMA between screen refresh >> DMAs, means a lot of small fragments queueing up, crazy callback >> chains etc .. not very informative to anyone. >> >> Time to get really into the datasheets.. > > Me too finally found time to look up that "Chrom-Art" "gfx accel" > thingy they PR. I mostly was interested if they arrogant enough to try > to conceal any low-level info about it, which is the norm for Cortex-A > SoCs. Nope, each bit is described. And "11.5.20 DMA2D AHB master timer > configuration register (DMA2D_AMTCR)" (p.365, DM00031020.pdf) says: > > Bits 15:8 DT[7: 0]: Dead Time > Dead time value in the AHB clock cycle inserted between two consecutive > accesses on the AHB master port. These bits represent the minimum > guaranteed number of cycles between two consecutive AHB accesses. > > > -- > Best regards, > Paul mailto:[email protected] ------------------------------------------------------------------------------ WatchGuard Dimension instantly turns raw network data into actionable security intelligence. It gives you real-time visual feedback on key security issues and trends. Skip the complicated setup - simply import a virtual appliance and go from zero to informed in seconds. http://pubads.g.doubleclick.net/gampad/clk?id=123612991&iu=/4140/ostg.clktrk _______________________________________________ libopencm3-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/libopencm3-devel
