On Sat, 1 Feb 2014, skeezix wrote:
# "Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled
# memory) data RAMUp to 192+4 Kbytes of SRAM including 64- Kbyte of CCM
# (core coupled memory) data RAM"
#
# Which is to say, SRAM 112K, SRAM 16K, and CCM 64K. There is no
# SRAM3 on the F405.
You know, the problem for me is GPIOs _and_ SRAM; they're all on
AHB1, along with DMA 1 and 2. So basicly any time I want to use any GPIO,
while DMA is going on, my image will glitch. Anytime I load SRAM1 during
DMA, it'll glitch.
FSMC is on AHB3, interestingly.. so I could perhaps tie into the
Z80 RAM chip, and with timing games access the RAM there and communicate
via RAM. Keep a action log in a buffer in memory, so the Z80 can issue
instructions in RAM. Then my main loop can just take a peek at RAM and
away it goes. (The Z80 clock may actually be driven by a timer in the
STM32 here so that is is software adjustable.. in which case I can just
hit the RAM after the clock ticks, or suspend the clock some number of
uSecs every scanline, whatever.)
The U(S)ARTs and I2C are on another bus as well, so the
intermediary chip would work fine as well. Could have DMA1 from USART to
SRAM2, and have the 16K there work as an action log as well.
I'll have to meditate on it; the self imposed rule of talking to a
z80 is the real problem here, since it lacks i2c/etc.
I'll take it off the mailing list for a few days while I wrap my
head around it; no need to derail the list any more than I have :)
But feel free to write back (perhaps directly to me?) if you think
FSMC to mount the z80 ram might be a neat hack.
jeff
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