For VGA, its busy much of the time .. Offhand I forget the details but the dma 
is probably busy 75% of the time or more.

The other device I'm talking to - for fun - is a Z80 which doesn't really have 
peripherals per se, just a bus. A z180 has uart though (and a z80 can use a SIO 
say, to get a uart); I've considered it but that would be pretty slow bandwidth 
as well .. Say 38kbits/sec .. 

I am using fifo.

I need to look up details .. But iirc the f405 haz 192k se as f429 disco; isn't 
it 112K main sram, maybe 16Kb sram2 and 64Kb ccm? Maybe ccm is counted separate 
.. If there is another 64KB on a different bus to main sram1 I might be in 
luck. My framebuffer is around 64K.

One thought I had (without looking into sram2 and sram3 at all yet) is .. 
During hsync, try to blit over a chunk to sram2 and dma from there, so even if 
its 16KB it should buy me some relief.

Weekend is family time, not much hacking time, so will read up a bit at 
midnight if I can :)

Thanks for your ideas!

--
Have you played Atari today?

> On Feb 1, 2014, at 4:27 PM, Michael Smith <[email protected]> wrote:
> 
> 
> A couple of things:
> 
> - Have you sized your DMA transactions so that you have some idea of how much 
> internal bandwidth you’re actually using? This can help you decide whether 
> you’re tight on bandwidth or whether there’s a latency issue that needs to be 
> addressed.
> 
> - If you are trying to communicate with other devices and you’re tight on 
> bandwidth, a combination of a USART (possibly in synchronous mode) and DMA 
> priority might help.
> 
> - Have you enabled the DMA controller FIFO? If you’re not up against the wall 
> for bandwidth, this can win you some insulation against latency.
> 
> - Can you fit all your frame buffer in SRAM2 (40x/41x) or SRAM3 (42x/43x)? 
> They are separate slaves off the bus matrix, so as long as you keep the CPU 
> out of them while you are DMAing, you will see less contention.
> 
> 
>> On 31 Jan 2014, at 10:31 pm, skeezix <[email protected]> wrote:
>> 
>> On Fri, 31 Jan 2014, Jeff Mitchell wrote:
>> 
>> # Excellent and many thanks! This will be enormously useful!
>> 
>>    .. and it was; I was able to get an order of magnitude increase in 
>> processing with this trick.
>> 
>>    The DMA problem is still quite a nuisance though; there is other 
>> work to be done.. and just toggling a GPIO pin causes VGA image distortion 
>> by colliding with the DMA. I can toggle a GPIO or read a GPIO during 
>> hsync, or vsync/vblank period. But if some other device sends something to 
>> the stm32, and theres an interupt on the gpio pin to catch it, I'm going 
>> ot have image distortion just to check the gpio values. (The interupt 
>> itself is okay.)
>> 
>>    I can try to do trickery such as receive the pin interupt, set a 
>> volatile flag, and then in the next hsync pull in the gpio state. This 
>> works, but then limits you to receiving only about 30,000 hits per second 
>> which is really not all that high (if you're streaming data between chips, 
>> via bitbang .. or don't want to miss the incoming data before it changes 
>> again; could maybe do i2c/etc, but the chips I'm talking to don't do 
>> any of that.. so I'd have to drop in an avr8 or stm8 or shift register 
>> chain or something, to serialize the incoming requests or change its 
>> protocol.. ugh!)
>> 
>>    Next up.. check the ref guide to see if possibly some GPIOs are on 
>> different buses relative to RAM, or anything like that; with lucky 
>> choices, is it possible to read/write a GPIO without getting in the way of 
>> DMA2 hitting GPIO and RAM.. otherwise, up to serious timing games :/
>> 
>>    Fun fun fun :)
>> 
>>        jeff
>> 
>> --
>> If everyone would put barbecue sauce on their food, there would be no war.
>> 
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