On Wed, 4 Jun 2003, Oliver Neukum wrote: > It seems to me that this union needs a cacheline of its own for > noncoherent architectures. The rest looks good.
Oliver: I would appreciate it if you (or anyone else) could post or provide a pointer to a good discussion that explains all the important issues involved in DMA coherency and cache interactions. These are tricky topics with a lot of subtleties. So here, for example, to what extent does it matter that the buffer is not allocated separately? Would moving it to the start of the whole kmalloc'ed structure solve the problem? Is this a question of each DMA master having to write in units of entire cachelines, thereby interfering with whatever data the CPU happens to store in the same cachelines? And does this also mean that it's effectively impossible to dynamically allocate any region smaller than a cacheline? Alan Stern ------------------------------------------------------- This SF.net email is sponsored by: Etnus, makers of TotalView, The best thread debugger on the planet. Designed with thread debugging features you've never dreamed of, try TotalView 6 free at www.etnus.com. _______________________________________________ [EMAIL PROTECTED] To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
