Am Mittwoch, 4. Juni 2003 20:58 schrieb Alan Stern:
> On Wed, 4 Jun 2003, Oliver Neukum wrote:
> > It seems to me that this union needs a cacheline of its own for
> > noncoherent architectures. The rest looks good.
>
> Oliver:
>
> I would appreciate it if you (or anyone else) could post or provide a
> pointer to a good discussion that explains all the important issues
> involved in DMA coherency and cache interactions. These are tricky topics
> with a lot of subtleties.
I wish I had one myself.
> So here, for example, to what extent does it matter that the buffer is not
> allocated separately? Would moving it to the start of the whole
> kmalloc'ed structure solve the problem?
No.
> Is this a question of each DMA master having to write in units of entire
> cachelines, thereby interfering with whatever data the CPU happens to
> store in the same cachelines?
No, the other way round. The CPU writes whole cachelines. This corrupts
parts of a cacheline not up to date in the CPU's cache.
> And does this also mean that it's effectively impossible to dynamically
> allocate any region smaller than a cacheline?
Yes.
Regards
Oliver
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