> The second restriction is that some architectures don't maintain their
> cache coherently when DMA takes place. This means that input buffers
> _must_ be allocated in a region containing no data the CPU will touch
> during the input operation. For if the CPU touches data D lying in the
> same cacheline as input buffer B while the input operation is underway,
> the old contents of B will get loaded into the cache along with D.
> Then after the input completes, when the CPU tries to read the new data in
> B it will see the stale contents in the cache instead.
Worse, if you dirty the cacheline. Old content can be written back
destroying data already DMAed in.
Regards
Oliver
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