David Brownell wrote:
Except that the UHCI spec is clear that in a given QH (or TD), only one word is modified and the others are read-only. So I see no way that "real UHCI" would ever write more than one 32-bit word at a time. Whose UHCI silicon is this, and do you know for a fact that something is doing a PCI burst write?
Indeed, but that's doesn't mean it doesnt'...
I don't know that all the chip are exactly doing. We would need a bus analyser or something like that to know
I don't know if it's the problem or not (yet) but that could be a possibility.
How can the dma_alloc_coherent() implementation be correct if the memory it returns has such an obvious cache effect? The definition of that routine says the memory returned has no such cache effects. Yet there they are -- cache effects. Something's wrong there.
Well, that's indeed a good question.
One I want to see answered, since it seems like the alloc_coherent() implementation on that one platform is most likely broken ... since it's implementing alloc_noncoherent() instead. There _are_ platforms that can't implement coherent memory. And for now, they have a hard time with USB.
Yes, there are. But, this one do.
There is pb on G3 but not on G4. However, Theses CPUs (should) have the same cache cohenrecy behaviour. Then it makes me think that the problem could not be cache cohenrecy related.
Nevertheless, I don't think it's a good idea to mix "so close" hardware and software field. Even, if it works it should be a bit slower as the NB may have to "merge" the two value.
It's a fine thing to have the fields near what the HC writes be read-only as much as possible. But with memory that's coherent, that shouldn't affect correctness.
That's a weird problem anyway, (weirder than I though!). But, the truth maybe be out of there (I hope this traslation from french is ok).
That's all for today anyway...
Bye
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