> > If the QH memory were truly "coherent", that patch could never > > matter. Someone who knows that CPU better should probably > > answer more detailed questions. For example, I'd think that > > using uncached mappings for that memory should ensure that the > > accesses are "coherent" enough. > > > > IMO, depending of the CPU/NorthBridge, the platfrom can or can't support > partial write to a cache-line if the CPU as a modified cache line.
Do you mean that the host controller is writing an entire cache line's worth of data (wiping out the software part of the QH), but in a cache coherent way? i.e. cache coherency has nothing to do with whether DMA writes part or all of a cache-line at a time? What gets written after the hardware part of the QH by the way? Some random junk from the host-controller's memory? Thanks a lot, Duncan. ------------------------------------------------------- This SF.Net email is sponsored by The 2004 JavaOne(SM) Conference Learn from the experts at JavaOne(SM), Sun's Worldwide Java Developer Conference, June 28 - July 1 at the Moscone Center in San Francisco, CA REGISTER AND SAVE! http://java.sun.com/javaone/sf Priority Code NWMGYKND _______________________________________________ [EMAIL PROTECTED] To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
