David Brownell wrote:
> > I'm reading it as: on the PPC boxes in question, > dma_alloc_coherent() -- used indirectly to allocate > the memory in question -- is returning memory that > doesn't work as required by the text I quoted. > > Specifically, caching effects DO exist, ones where > the CPU's L1 cache line size matters. X86 systems > use cache snooping to let coherent memory be cached. > >
I think most of the PowerPC machine works just like the x86.
About this one (Pegasos II), it does support cache coherency/bus snooping.
So, IMO, dma_alloc_coherent is correct (otherwise, nothing would work, and we would need to rewrote each Linux driver ...)
>> Is the problem that the device (or maybe PCI bridge) is caching data and
>> then overwriting stale data to the software portion of the QH descriptor?
>
>
> If the QH memory were truly "coherent", that patch could never > matter. Someone who knows that CPU better should probably > answer more detailed questions. For example, I'd think that > using uncached mappings for that memory should ensure that the > accesses are "coherent" enough. >
IMO, depending of the CPU/NorthBridge, the platfrom can or can't support partial write to a cache-line if the CPU as a modified cache line.
Here, we had no problem on IBM 750CXe (G3) but serious hangs on Motorola MPC7447 (G4).
> have a clearly specified sequence to violate, the HCD might > be missing some barriers, and so on. >
Possible. I though the problem was reordering at the beginning (the G3 doesn't reorder but the G4 does). However, I haven't find any weakness in the UHCI driver about that.
Bye
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