Nicolas DET wrote:
David Brownell wrote:
>
> I'm reading it as: on the PPC boxes in question,
> dma_alloc_coherent() -- used indirectly to allocate
> the memory in question -- is returning memory that
> doesn't work as required by the text I quoted.
>
> Specifically, caching effects DO exist, ones where
> the CPU's L1 cache line size matters. X86 systems
> use cache snooping to let coherent memory be cached.
I think most of the PowerPC machine works just like the x86.
About this one (Pegasos II), it does support cache coherency/bus snooping.
So, IMO, dma_alloc_coherent is correct (otherwise, nothing would work,
and we would need to rewrote each Linux driver ...)
But you DID need to change a driver, since it's behaving
differently. Why are you arguing that it's correct?
> If the QH memory were truly "coherent", that patch could never
> matter. Someone who knows that CPU better should probably
> answer more detailed questions. For example, I'd think that
> using uncached mappings for that memory should ensure that the
> accesses are "coherent" enough.
>
IMO, depending of the CPU/NorthBridge, the platfrom can or can't support
partial write to a cache-line if the CPU as a modified cache line.
How can the dma_alloc_coherent() implementation be correct if the
memory it returns has such an obvious cache effect? The definition
of that routine says the memory returned has no such cache effects.
Yet there they are -- cache effects. Something's wrong there.
Also: http://marc.theaimsgroup.com/?t=108083642300009&r=1&w=2
suggests that some PPC platforms are exposing more limitations
of the new-in-2.6 "generic" DMA calls; this could be another.
I thought there a rewrite of the PPC generic DMA code recently
merged ... does that affect the problem you're seeing?
- Dave
Here, we had no problem on IBM 750CXe (G3) but serious hangs on Motorola
MPC7447 (G4).
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