Alan Cox wrote:
It makes me nervous. The first thing I see is the question about ordering between posted writes to the IntEnable reg in PCI space and the software register. The second thing is returning IRQ_NONE causing the "screaming interrupt" warning.
outw() takes care of the ordering. by the way, I had "eieio" in mind.
I'm not saying you are wrong, its the kind of code that I really really would never write unless it had huge payback.
Ok. Anyway, that doesn't really matter the important part of the patch is the aligement.
You do hang in the IRQ handler in this case until the drop of the IRQ reaches the far end of the link because it is level triggered.
At the beginning of the interrupt handler there is: >outw(0, io_addr + USBINTR);
It should set to "high" (so "no interrupt") the PCI/APIC interrupt line, but keep it "low" in the UHCI chipset until it's cleared.
Of course, I undersdant your point of view. This part of the patch could be ignored until it's really proved to be reliable on all architecture but the alignment part is not trivial IMO and should not hurt any other platform.
By the way, I'm happy to speak about that. It's a very interesting discussion to me. :-)
Bye
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