From: Marek Olšák <[email protected]>
---
src/gallium/drivers/radeon/r600_pipe_common.h | 7 -----
src/gallium/drivers/radeon/r600_query.c | 2 +-
src/gallium/drivers/radeonsi/si_hw_context.c | 2 +-
src/gallium/drivers/radeonsi/si_pipe.h | 32 +++++++++++++----------
src/gallium/drivers/radeonsi/si_state.c | 8 +++---
src/gallium/drivers/radeonsi/si_state_draw.c | 6 ++---
src/gallium/drivers/radeonsi/si_state_streamout.c | 1 -
7 files changed, 27 insertions(+), 31 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 5fcaa10..c052a54 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -45,27 +45,20 @@
#include "util/u_threaded_context.h"
struct u_log_context;
#define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV <<
0)
#define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV <<
1)
#define R600_RESOURCE_FLAG_FORCE_TILING
(PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
#define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV <<
3)
#define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV <<
4)
-#define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
-/* Pipeline & streamout query controls. */
-#define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
-#define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
-#define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3)
-#define R600_CONTEXT_PRIVATE_FLAG (1u << 4)
-
/* Debug flags. */
enum {
/* Shader logging options: */
DBG_VS = PIPE_SHADER_VERTEX,
DBG_PS = PIPE_SHADER_FRAGMENT,
DBG_GS = PIPE_SHADER_GEOMETRY,
DBG_TCS = PIPE_SHADER_TESS_CTRL,
DBG_TES = PIPE_SHADER_TESS_EVAL,
DBG_CS = PIPE_SHADER_COMPUTE,
DBG_NO_IR,
diff --git a/src/gallium/drivers/radeon/r600_query.c
b/src/gallium/drivers/radeon/r600_query.c
index 8a000e2..e1239ae 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -1815,21 +1815,21 @@ static void r600_render_condition(struct pipe_context
*ctx,
*/
rctx->render_cond = NULL;
ctx->get_query_result_resource(
ctx, query, true, PIPE_QUERY_TYPE_U64, 0,
&rquery->workaround_buf->b.b,
rquery->workaround_offset);
/* Settings this in the render cond atom is too late,
* so set it here. */
rctx->flags |= rctx->screen->barrier_flags.L2_to_cp |
- R600_CONTEXT_FLUSH_FOR_RENDER_COND;
+ SI_CONTEXT_FLUSH_FOR_RENDER_COND;
rctx->render_cond_force_off = old_force_off;
}
}
rctx->render_cond = query;
rctx->render_cond_invert = condition;
rctx->render_cond_mode = mode;
rctx->set_atom_dirty(rctx, atom, query != NULL);
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c
b/src/gallium/drivers/radeonsi/si_hw_context.c
index 2d7f6a7..f163e50 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -184,21 +184,21 @@ static void si_begin_cs_debug(struct si_context *ctx)
void si_begin_new_cs(struct si_context *ctx)
{
if (ctx->is_debug)
si_begin_cs_debug(ctx);
/* Flush read caches at the beginning of CS not flushed by the kernel.
*/
if (ctx->b.chip_class >= CIK)
ctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
SI_CONTEXT_INV_ICACHE;
- ctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
+ ctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS;
/* set all valid group as dirty so they get reemited on
* next draw command
*/
si_pm4_reset_emitted(ctx);
/* The CS initialization should be emitted before everything else. */
si_pm4_emit(ctx, ctx->init_config);
if (ctx->init_config_gs_rings)
si_pm4_emit(ctx, ctx->init_config_gs_rings);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index fd9ba3a..bdf146f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -41,44 +41,48 @@
/* The base vertex and primitive restart can be any number, but we must pick
* one which will mean "unknown" for the purpose of state tracking and
* the number shouldn't be a commonly-used one. */
#define SI_BASE_VERTEX_UNKNOWN INT_MIN
#define SI_RESTART_INDEX_UNKNOWN INT_MIN
#define SI_NUM_SMOOTH_AA_SAMPLES 8
#define SI_GS_PER_ES 128
/* Alignment for optimal CP DMA performance. */
#define SI_CPDMA_ALIGNMENT 32
+/* Pipeline & streamout query controls. */
+#define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
+#define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
+#define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
/* Instruction cache. */
-#define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
+#define SI_CONTEXT_INV_ICACHE (1 << 3)
/* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
-#define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1)
+#define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
/* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
-#define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
+#define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
/* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC
L2 */
-#define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
+#define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
/* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
* invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
-#define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4)
+#define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
/* Writeback & invalidate the L2 metadata cache. It can only be coupled with
* a CB or DB flush. */
-#define SI_CONTEXT_INV_L2_METADATA (R600_CONTEXT_PRIVATE_FLAG << 5)
+#define SI_CONTEXT_INV_L2_METADATA (1 << 8)
/* Framebuffer caches. */
-#define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
-#define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
-#define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8)
+#define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
+#define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
+#define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
/* Engine synchronization. */
-#define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
-#define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
-#define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
-#define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12)
-#define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13)
+#define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
+#define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
+#define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
+#define SI_CONTEXT_VGT_FLUSH (1 << 15)
+#define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
#define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
#define SI_PREFETCH_LS (1 << 1)
#define SI_PREFETCH_HS (1 << 2)
#define SI_PREFETCH_ES (1 << 3)
#define SI_PREFETCH_GS (1 << 4)
#define SI_PREFETCH_VS (1 << 5)
#define SI_PREFETCH_PS (1 << 6)
#define SI_MAX_BORDER_COLORS 4096
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index ca32afd..cdab8ea 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1326,25 +1326,25 @@ static void *si_create_db_flush_dsa(struct si_context
*sctx)
}
/* DB RENDER STATE */
static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
{
struct si_context *sctx = (struct si_context*)ctx;
/* Pipeline stat & streamout queries. */
if (enable) {
- sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
- sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
+ sctx->b.flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
+ sctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS;
} else {
- sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
- sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
+ sctx->b.flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
+ sctx->b.flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
}
/* Occlusion queries. */
if (sctx->occlusion_queries_disabled != !enable) {
sctx->occlusion_queries_disabled = !enable;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
}
static void si_set_occlusion_query_state(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 530137e..7330bf4 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1085,25 +1085,25 @@ void si_emit_cache_flush(struct si_context *sctx)
si_emit_surface_sync(rctx, cp_coher_cntl |
S_0085F0_TCL1_ACTION_ENA(1));
cp_coher_cntl = 0;
}
}
/* If TC flushes haven't cleared this... */
if (cp_coher_cntl)
si_emit_surface_sync(rctx, cp_coher_cntl);
- if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
+ if (rctx->flags & SI_CONTEXT_START_PIPELINE_STATS) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
EVENT_INDEX(0));
- } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
+ } else if (rctx->flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
EVENT_INDEX(0));
}
rctx->flags = 0;
}
static void si_get_draw_start_count(struct si_context *sctx,
const struct pipe_draw_info *info,
@@ -1426,21 +1426,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
/* If we have to wait for idle, set all states first, so that
all
* SET packets are processed in parallel with previous draw
calls.
* Then upload descriptors, set shader pointers, and draw, and
* prefetch at the end. This ensures that the time the CUs
* are idle is very short. (there are only SET_SH packets
between
* the wait and the draw)
*/
struct r600_atom *shader_pointers = &sctx->shader_pointers.atom;
unsigned masked_atoms = 1u << shader_pointers->id;
- if (unlikely(sctx->b.flags &
R600_CONTEXT_FLUSH_FOR_RENDER_COND))
+ if (unlikely(sctx->b.flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
masked_atoms |= 1u << sctx->b.render_cond_atom.id;
/* Emit all states except shader pointers and render condition.
*/
si_emit_all_states(sctx, info, masked_atoms);
si_emit_cache_flush(sctx);
/* <-- CUs are idle here. */
if (!si_upload_graphics_shader_descriptors(sctx))
return;
diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c
b/src/gallium/drivers/radeonsi/si_state_streamout.c
index 0c20c58..3e83243 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -342,21 +342,20 @@ void si_emit_streamout_end(struct si_context *sctx)
/* Zero the buffer size. The counters (primitives generated,
* primitives emitted) may be enabled even if there is not
* buffer bound. This ensures that the primitives-emitted query
* won't increment. */
radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
16*i, 0);
t[i]->buf_filled_size_valid = true;
}
sctx->streamout.begin_emitted = false;
- sctx->b.flags |= R600_CONTEXT_STREAMOUT_FLUSH;
}
/* STREAMOUT CONFIG DERIVED STATE
*
* Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
* The buffer mask is an independent state, so no writes occur if there
* are no buffers bound.
*/
static void si_emit_streamout_enable(struct r600_common_context *rctx,
--
2.7.4
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